Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
While designing my own 16-bit CPU I wonder how the register-register XCHG instruction is executed internally. From computer science I know the DLX which doesn't provide XCHG and therefore doesn't need to access two registers in write-back (would this even be possible?), but only the destination register. I guess this isn't done in one cycle, right?
Thx in advance
You have a couple of options.
You can add the extra hardware in the data path to allow it to occur in one cycle. This has difficulties in a pipelining architecture because a dual port register file is often used for simultaneous reads and writes for the different stages. This adds the need for a second write port. Without this, there really is not a way to prevent a bubble in the pipeline from eventually having to occur.
A generally better option is to simply have a multicycle instruction. The important thing here is to make sure you prevent any other operation such as interrupts or other bus masters (in the case of a memory swap) from make this appear non-atomic.
The multicycle instruction option is what is generally done. For example, the ARM SWP and the XCHG instructions are multicycle.
dmov r0,r1 ["delayed move"] would cause r1 to be stored in r0 but the store wouldn't take place until after the next instruction's operand fetches [which would receive data from registers, rather than from forwarding circuitry]. A delayed-move and delayed-load would allow easy two-instruction swaps between two registers, or between a register and memory.
\$\endgroup\$
Another option is to mess with the register addressing, I suspect this is how the Z80 EXX opcode swaps register banks in 4 cycles. it's possibly also how EX DE,HL swaps two register pairs registers in 4 cycles on the
same micro. the same cycle count it takes to copy one 8-bit register to another.
This instruction is most likely implemented using register renaming. With register renaming, the register contents are assigned to registers names with tags. This makes swapping registers very easy - just swap the tags. No need for multiple register writes in the same cycle.
This is how the Z80 implemented the EX instruction. See: http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html
Swapping registers through register renaming
The Z80 has several instructions to swap registers or register sets. The EX DE, HL instruction exchanges the DE and HL registers. The EX AF, AF' instruction exchanges the AF and AF' registers. The EXX instruction exchanges the BC, DE, and HL registers with the BC', DE', and HL' registers. These instructions complete very quickly, which raises the question of how multiple 16-bit register values can move around the chip at once.
It turns out that these instructions don't move anything. They just toggle a bit that renames the appropriate registers. For example, consider exchanging the DE and HL registers. If the DE/HL bit is set, an instruction acting on DE uses the first register and an instruction acting on HL uses the second register. If the bit is cleared, a DE instruction uses the second register and a HL instruction uses the first register. Thus, from the programmer's perspective, it looks like the values in the registers have been swapped, but in fact just the meanings/names/labels of the registers have been swapped. Likewise, a bit selects between AF and AF', and a bit selects between BC, DE, HL and the alternates. In all, there are four registers that can be used for DE or HL; physically there aren't separate DE and HL registers.
The hardware to implement register renaming is interesting, using four toggle flip flops.[7] These flip flops are toggled by the appropriate EX and EXX instructions. One flip flop handles AF/AF'. The second flip flop handles BC/DE/HL vs BC'/DE'/HL'. The last two flip flops handle DE vs HL and DE' vs HL'. Note that two flip flops are required since DE and HL can be swapped independently in either register bank.
