I am using TMS320F28035 in SPI Master mode. Where I have to transmit 8 Bit data to the slave device and have to read 16-bit data out of the slave device after completion of data transfer from master to slave. So total of 24 SPICLK cycles to carry out complete communication.
Since I have to read 16-bit data from the slave, master device should keep clock running for 24 cycles. But clock stops as soon as the data in SPITXBUF transmitted. To acquire at least some data from the slave I am keeping clock running by placing 16-bit data in the SPITXBUF so that 8 bits of useful data and 8-bits of garbage just to hold the clock total 16 cycles. During this period I am able to read 8 bits of data from the slave.
Now the question is how should I hold the clock running for 8 more cycles to read remaining 8-bits from slave?