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I am using TMS320F28035 in SPI Master mode. Where I have to transmit 8 Bit data to the slave device and have to read 16-bit data out of the slave device after completion of data transfer from master to slave. So total of 24 SPICLK cycles to carry out complete communication.

Since I have to read 16-bit data from the slave, master device should keep clock running for 24 cycles. But clock stops as soon as the data in SPITXBUF transmitted. To acquire at least some data from the slave I am keeping clock running by placing 16-bit data in the SPITXBUF so that 8 bits of useful data and 8-bits of garbage just to hold the clock total 16 cycles. During this period I am able to read 8 bits of data from the slave.

Problem:

Now the question is how should I hold the clock running for 8 more cycles to read remaining 8-bits from slave?

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  • \$\begingroup\$ Haven't used this part but I'd guess either poll its tx buffer empty bit or enable interrupts so you know when the tx buffer is empty. Then write another byte. The shift register that is actually putting bits on the line won't be empty yet and hopefully that keeps the transaction going. \$\endgroup\$ – Some Hardware Guy Jan 31 '15 at 12:54
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    \$\begingroup\$ The SPI protocol is very simple. You need to transmit a byte for every byte you want to receive. When there's nothing useful that needs to be sent, it's normal to send "dummy" bytes of all-zeros or all-ones. \$\endgroup\$ – Dave Tweed Jan 31 '15 at 13:01
  • \$\begingroup\$ Thanx dave solved the problem \$\endgroup\$ – rahulb Jan 31 '15 at 14:28

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