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I have heard/read in the past that people are not looking at constructing integrated circuits as stacks of individual dies, connected together inside a package. This has been done for example where a die for pure memory was connected separately to a bigger circuit of digital circuit within the physical package before the device leaves the factory. This makes customization easier and cheaper.

However, I do not read about this methodology becoming pervasive.

Why are the reasons that "3D ICs" have not become pervasive yet?

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  • \$\begingroup\$ I haven't heard of these before, but it sounds like they'd be a lot more expensive to manufacture. I don't think most people want to pay much extra for a slightly smaller footprint. \$\endgroup\$
    – Greg d'Eon
    Commented Jan 31, 2015 at 15:48
  • \$\begingroup\$ I'm guessing it's a heat problem, but I have no idea. \$\endgroup\$ Commented Jan 31, 2015 at 15:59
  • \$\begingroup\$ Wikipedia has a pretty good summary of what the problems are: en.wikipedia.org/wiki/… \$\endgroup\$ Commented Jan 31, 2015 at 16:07
  • \$\begingroup\$ The impression I have now by reading all this is that heat dissipation is the main issue here. Does this mean that once we move onto devices that use photons to transmit information, "3D ICs" will come closer to reality? \$\endgroup\$
    – quantum231
    Commented Jan 31, 2015 at 22:58
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    \$\begingroup\$ 3D ICs demand much higher reliability, since a fault in them is not easily serviceable and would require discarding entire package including non-faulty layers. Higher heat also requires increasing DRAM refresh rate for maintaining data integrity which costs power. See my survey for more details. \$\endgroup\$
    – user984260
    Commented Sep 19, 2015 at 21:02

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It depends what you mean by 3D. The are various integration levels. Some are more difficult than others. Here's a (somewhat optimistic) outline taken from http://thor.inemi.org/webdownload/2014/Eurotherm_061914.pdf

enter image description here

The outline above is actually a bit old; it was first published in a 2010 paper: http://dx.doi.org/10.1109/ECTC.2010.5490828

The pie in the middle of that slide is supposedly fairly big already:

[In 2011], the market value of all the devices using TSV packaged in 3D in the 3DIC or 3D-WLCSP platforms (CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7B. It will represent 9% of the total semiconductor value by 2017, hitting almost $40B.

Another estimate is a bit less optimistic though:

Globally, 3DICs market was valued at USD 2.40 billion in 2012 and is forecast to grow at 18.1 percent CAGR from 2013 – 2019.

For low-power 3D memory devices, JEDEC already has a standard, JESD229 "Wide I/O Single Data­Rate", which gives 2x the bandwidth of LPDDR2 while keeping the same power consumption [ref]. For high-performance 3D memory, there's non-JEDEC standard, Hybrid Memory Cube which has fairly good industry backing (Micron, Samsung, Intel). Intel has announced that Knights Landing (to appear in the 2nd half of this year) is going to use HMC. For high-performance 3D RAM, JEDEC instead standardized JESD235 "High Bandwidth Memory" which is backed by AMD, Hynix and Nvidia. Nvidia Pascal to appear in 2016 or so is supposedly going to use this HBM.

If you're talking about CPUs or other chips generating a lot heat... it's going to be much harder to make them in 3D stacks because of the difficulty in getting rid of the heat from the inner layers. In 2008 IBM Research published their experiments with water running through capillarity micro-channels inside a 3D die [ref] see also video (of more recent/2012 progress with that). This is obviously tricky to get working at a competitive price point. I have no idea if/when they plan to commercialize something like that, and even then it they'd probably target their mainframes first.

And also on the issue of heat, I've been wondering why I can't find any mentions of design wins for Wide IO (the low-power 3D memory). I can't be sure of the real reasons behind its market flop, but it turns out that even though it uses less power than PoP (package-on-package) solutions, due to its real 3D structure (using TSV - through-silicon vias) Wide IO actually heats up faster than a PoP solution, especially with the SoC underneath giving it some "help". This is admitted in a presentation by its promoters; see slide 15. (N.B.: there's some well-founded, X-rays-based speculation that the Playstation Vita uses Wide I/O, but nothing has been officially confirmed.) There's also a "Wide IO 2" JEDEC standard JESD229-2 now. I can't find any mentions of adoption in devices for that either, but this it is rather new, so time will tell. Anyway, the point I'm trying to make is that even in low-power devices, 3D chips can have significant heating issues.

As for the current 3D market, I think a lot of it (though I can't say what proportion exactly) is in the illuminated CMOS sensors (both front- and back-illumnated) that are present in many cameras and even smart phones. There's nice visual presentation of many of these chips with actual photos and even some profile X-rays (on several slides, so I'm not pasting it here) in a Semicon Taiwan 2012 talk; it also has photos of more obscure current 3D applications like MEMS accelerometers so forth.

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There's a couple reasons for it not being pervasive yet. If you're stacking dies, you're multiplying the physical die area by the number of layers. The more of the physical wafer you take up using this method, the less parts/wafer and therefore less $/wafer you're getting.

Another reason is that many integrated circuits fit just fine within the confines of a single layer IC. If they need more space they can usually go to a process shrink without any problems. So the only real place for this is in really complicated circuits such as SoC's used within tiny form factors like phones.

One more reason is that once you stack layers, you have to have good communication between layers. Connections between layers will be physically larger than connections between normal components on a single die so you have to work around this complication and potential slowdown between layers on a multi-layer die.

Basically, there's no free-lunch. This is a work-around to Moore's Law but it's not easy or simple to execute. Normal ASIC's are hard enough to make right. Adding in layers just makes it even more complicated, costly, and difficult to engineer.

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    \$\begingroup\$ One other big gotcha is that except in low power operation cooling becomes much harder as the stack of chips gets taller. \$\endgroup\$ Commented Jan 31, 2015 at 17:46

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