In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. In this example a smaller device was chosen 'small' enough to view in ISE.

What are the parts shown by the arrows please. And are the yellow and orange bits the same?

fpga implementation

  • \$\begingroup\$ Which chip are you using? \$\endgroup\$
    – Dave Tweed
    Jan 31, 2015 at 22:05
  • \$\begingroup\$ @DaveTweed Spartan 3, XC3-S50 \$\endgroup\$
    – slasher53
    Jan 31, 2015 at 22:53

1 Answer 1


Using the terminology found in the datasheet (see Figure 1):

  • blue arrow: CLB (configurable logic block). This contains four "slices", where one slice comprises two LUTs (lookup tables) and two flip-flops (see Figures 11 and 12).
  • white arrow: This area contains both BRAM (block static RAM) and multipliers.
  • yellow and orange arrows: IOB (Input/Output Block) (see Figure 7)

The thin blue trace that runs all the way to the top of the diagram and then loops to the right and down again is your clock. It originates at the tiny block in the bottom row, which is a DCM (digital clock manager), and it passes through a global clock buffer on its way up.

While in the chip editor, you can zoom in on each of these blocks and even peek inside them to see exactly which resources are being used to implement your design.

  • \$\begingroup\$ I think the blue arrow is pointing to the routing switch box isn't it? The CLB resources (LUT+FF) are the 2 pairs of 2 (slightly offset) tiny grey boxes. The relative size is probably not far off reality - somebody from Xilinx once said they were selling "mainly routing with some logic interspersed"! \$\endgroup\$ Feb 2, 2015 at 11:57
  • \$\begingroup\$ @MartinThompson: Yes, that's technically correct. A CLB is slices plus routing switches. \$\endgroup\$
    – Dave Tweed
    Feb 2, 2015 at 12:10

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