2
\$\begingroup\$

The task is to implement a 4-bit shift register with parallel input and serial output using JK flip-flops and standard logic gates. The solution is below:

enter image description here

This is what happens on the output:

enter image description here

I don't understand what the SHIFT/LOAD is. Can you please explain what happens in this register if we want to input the number 1010?

\$\endgroup\$
2
\$\begingroup\$

According to the schematic, SHIFT/LOAD represents mode.
If pin SHIFT/LOAD is set to

  • logic 1 the SR will move it's values. (Q0 will shift in Q1, Q1 in Q2, Q2 in Q3, Q3 in O3)
  • logic 0 the SR will read values from pins (D1=Q1,D2=Q2,D3=Q3, Q0/D0 does not depend on SHIFT/LOAD pin)

If we want to input 1010 in the shift register, we will need to use one of two methods.

Serial way:

  1. Set SHIFT/LOAD to 0 (t=1)
  2. Set D0 to 0 (t=1)
  3. SHIFT/LOAD = 1 (Q0 goes in Q1) (t=2)
  4. Set D0 to 1 (in the following clock cycle, Q1 goes in Q2 and Q0 into Q1) (t=2)
  5. D0=0 (Q2 in Q3, Q1 in Q2, Q0 in Q1) (t=3)
  6. D0=1 (Q3 in O3, Q2 in Q3, Q1 in Q2, Q0 into Q1) (t=4)

Parallel way:

  1. Set SHIFT/LOAD = 1 (t=1)
  2. Set D0=1, D1=0, D2=1, D3=0. (t=2)
  3. SHIFT/LOAD = 1 (t=3)
  4. 1010 will be the output of the O3, but in opposite order 0101 (t=7~8)
\$\endgroup\$
  • \$\begingroup\$ But why do we need D1, D2 and D3 if all bits are input through D0. It should be a parallel input. I'm sorry if I'm mistaken, I started learning shift registers today. \$\endgroup\$ – A6SE Feb 1 '15 at 13:54
  • \$\begingroup\$ You are not mistaken, there are 2 ways of entering data in this schematic. \$\endgroup\$ – Triak Feb 1 '15 at 14:01
  • \$\begingroup\$ So, we can input all bits at once: D0=1, D1=0, D2=1, D3=0 and then change SHIFT/LOAD to 1 and keep it like this till all bits are shifted through Q3? \$\endgroup\$ – A6SE Feb 1 '15 at 14:03
  • 1
    \$\begingroup\$ Yes we can, but the circuit will get in the value from D0 in the other blank places shifted out. Until all bits are shifted through O3. \$\endgroup\$ – Triak Feb 1 '15 at 14:05
2
\$\begingroup\$

I don't understand what this SHIFT/LOAD is.

Each register has a 2-to-1 multiplexer in front of what is effectively its D input. This multiplexer determines whether the input is

  • the output of the previous register (thus implementing the SHIFT function)
  • the parallel input (thus implementing the parallel LOAD function)

(For the first register this would be the same thing, so to save pins & logic area this register has only one input.)

\$\endgroup\$
  • \$\begingroup\$ Would SHIFT/LOAD (0 for load, 1 for shift) represent the selection inputs of a multiplexer then, and the information inputs the output of a previous flip-flop and the new input. \$\endgroup\$ – A6SE Feb 1 '15 at 14:07
  • 1
    \$\begingroup\$ I think you say the same as I explained, but due to your use of English I am not fully sure. \$\endgroup\$ – Wouter van Ooijen Feb 1 '15 at 14:18
  • \$\begingroup\$ Yes, sorry, I'm not a native speaker. I think I understand now. Thanks. \$\endgroup\$ – A6SE Feb 1 '15 at 14:36

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.