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I am designing a board for a 12V automotive environment, with a variety of input voltage transients including load dump and permanent 24V over-voltage. I am using a TVS at the input to clamp to around 60V followed by a TI LM5060, a power supply supervisor, which in case of an over-voltage above 18V (or overcurrent) will cut off the power to my circuit using an external 60V MOSFET. The LM5060 datasheet specifies a 9.6 microsecond delay from the onset of a over-voltage condition to the MOSFET gate turning off. On the other side of the LM5060 I have my bulk capacitor and number of linear regulators and other ICs which at their input can tolerate up to around 30V (or 45V depending on what parts I choose).

So my question is, during that 9.6µs it takes for LM5060 to kick in, how can I ensure that nothing on its down-side gets fried? Is a sufficiently large bulk capacitor (220uF?) enough to absorb that transient? Or would I be better off using a small zener? How would I choose a value for this zener/capacitor?

If anyone knows of a better/cheaper alternative to LM5060, please let me know. I only need it to provide over-voltage protection up to around 60V.

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  • \$\begingroup\$ You can delay the input current arrival to LM5060 using a proper coil. \$\endgroup\$ – GR Tech Feb 2 '15 at 9:04
  • \$\begingroup\$ How much current does your circuit draw? There are several inexpensive techniques but they vary according to how much current they have to pass. \$\endgroup\$ – Dwayne Reid Feb 5 '15 at 6:17
  • \$\begingroup\$ my circuit draw a maximum of 1.4A. \$\endgroup\$ – lyxicon Feb 8 '15 at 7:38
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Just throwing this out there: Typical FET response is measured in nanoseconds.

schematic

simulate this circuit – Schematic created using CircuitLab

Vshutdown > VzZD1 + VgthFET1

If VzZD1 = 50V and VgthFET1 = 3V then Vshutdown > 53V

As shown, FET1 may (will try to) destroy itself to protect the load. Determine resistor sizes as follows:

R1 protects FET1  
(R2 > R1) ensures lower-impedance path through FET than load

Size R2 according to Ohm's law with Vout "grounded":

E = I * R
Edrop = Vin - Vout = 12V - 0V = 12V
R = Edrop / I
R = 12V / 1.4A = 8.57ohm

If Vzd1 = 12V and VgthFET1 = 3V, then Vshutoff = 15V:

Ir2 = E / R
Ir2 = 15V / 8.57ohm = 1.75A

FET1 will pass Vin - Vzd1 - VgthFET1 when active.
If R1 = 0 and Vin = 50V:

VdsFET1 = 50V - 12V - 3V = 35V
I = E / R
I = 35V / 25mOhm = 1400A //Zap!

If R1 = 4 ohm ("less" than R2) and Vin = 50V:

VdsFET1 = 50V - 12V - 3V = 35V
I = E / R
I = 35V / (4 + 25mOhm) = 8.70A
EdropR1 = 8.70A * 4Ohm = 34.8V
EdropFET = 8.70A * 0.025Ohm = 0.2V
P = I * E
PFET = 8.70A * 0.2V = 1.74W
PR1 = 8.70A * 34.8V = 302.76W //Warm
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  • \$\begingroup\$ I am not sure I understand. My circuit draws 1.4A. That means the voltage drop across the 200ohm resistor in your circuit will be be 1.4*200=280V!!! and R1 and that MOSFET would also have to a huge. \$\endgroup\$ – lyxicon Feb 8 '15 at 7:35
  • \$\begingroup\$ "Resistors need proper sizing" :P I added additional sizing information. \$\endgroup\$ – Jon Feb 11 '15 at 6:45
  • \$\begingroup\$ Also, if Vin = 12V, with a 200ohm resistor and a 200ohm load, each resistor would drop 6V @ 15mA. Since 200 is waaay to big, your load would be unable to "demand" 1.4A from it. 1.4A is the maximum you intend to request from the power supply. \$\endgroup\$ – Jon Feb 11 '15 at 6:54
  • \$\begingroup\$ Do Zener diodes not need to have a current flowing through them to actually drop a voltage? Without a pull down resistor between the Zener and ground I'm not sure how this would work? Maybe my understanding is wrong? \$\endgroup\$ – LeoR Feb 11 '15 at 11:51
  • \$\begingroup\$ To regulate a stable voltage, yes. For this purpose, we are just trying to dump over-voltage to ground and should only need to bias the gate for a moment. \$\endgroup\$ – Jon Feb 11 '15 at 12:35
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Although the question is three years old, no proper answer was given.

The LM5060 datasheet specifies a 9.6 microsecond delay from the onset of a over-voltage condition to the MOSFET gate turning off. So my question is, during that 9.6µs it takes for LM5060 to kick in, how can I ensure that nothing on its down-side gets fried?

"Delay from OVP Pin > OVPTH to GATE low" does not necessarily mean that during this interval output voltage rises considerably. The output voltage rise depends on charge pump operation, so you can calculated how much charge a feeble 24-uA pump can deliver into mosfet gate during 9.6 us (hint: 0.23 nC). With this quantity of charge injected Gate-Source voltage will rise for a fraction of volt (see mosfet gate charge diagram) so actually your down-side is safe.

Obviously Cdv/dt is another source of gate charge injection, and measures should be taken that injection is also insignificant during discussed interval.

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