I was asked to find the answer for this, it is a pretty vague question:

On a D Flip Flop, what is the Q' output? Look this up and write your answer in your pre-lab report.

I am trying to understand the circuit, it looks like Q' is what retains the previous value of Q when the clock is high. Can someone explain more about this to me?


Very fundamental thing. Flip-flops are composed of logic circuits that have cross coupled feedback such that they "hold" the last established state. These bi-stable circuits are often composed of inverting gate elements that invert twice around their cross coupled feedback to realize the latched state.

Simply the Q output is the output of one side of the bi-stable circuit. The Q' is the other output which, in the case of cases where inverted logic elements are used, ends up being the logical inversion of the Q output.

So if Q = 1 the Q' = 0. Likewise of Q = 0 the Q' = 1.

  • \$\begingroup\$ So I can say that Q' will contain the inverse of the value of D in the previous cycle and that is also the feedback used for Q in the present cycle? \$\endgroup\$ – JOX Feb 2 '15 at 1:29
  • \$\begingroup\$ Yes. There is no absolute requirement to bring this out to the pins of an IC, but in general a "pre-inverted" version of the Q output is so useful that it's brought out as a matter of course. \$\endgroup\$ – WhatRoughBeast Feb 2 '15 at 1:49
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    \$\begingroup\$ @JOX - You have to stop thinking of the Q' as a history element. For your typical 74xx74 type D flip flop that has both Q and Q' outputs it is simply that Q attains the value of the D input after the clock and the Q' attains the inverted value of the D input after the clock. Of course the D input must meet setup and hold time requirements for the particular FF in use. \$\endgroup\$ – Michael Karas Feb 2 '15 at 1:59
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    \$\begingroup\$ Normally the Q' output will be the inverse of the Q at least after a propagation delay following the clock. Things might be different if the FF has reset and set inputs and they're both active (The 74HC74 will have both outputs high as long as that condition exists). \$\endgroup\$ – Spehro Pefhany Feb 2 '15 at 4:45

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