# square wave generator on 20MHz

I need a circuit that generates rectangular waves. It shouldn't be lo-hi-lo-hi, but a random sequence of lo-hi-hi-hi-lo-lo is needed. It also has to oscillate like that, at at least 20MHz. I don't mind getting a special IC... Anything to make the job easier is fine by me.

Alright, I'm looking for really dead-easy ones and so thanks Nick for the solution. I'm also considering something possibly even smaller.

Maybe I can use an ordinary digital oscillator and then dynamically change its oscillating frequency (change in frequency also in terms of MHz), so that the level signals get dilated and compressed, giving the effect that we have randomly generated bitstreams. Though we have to set the targeted frequency (in this case, 20MHz), as the lower limit of changing the frequencies.

Something like this, an LTC6905 - http://cds.linear.com/docs/en/datasheet/6905fd.pdf (ok, not exactly cheap), and then vary the setting resistor in small increments/decrements randomly.

Of course there is a problem of randomly changing the resistance that is itself at least pseudo random. So it's back to square one. Any comments on this??

• random sequence; as in "truly random" or as in "arbitrary but repeatable sequence" Commented Feb 2, 2015 at 10:04
• Closely related question: electronics.stackexchange.com/questions/30521/… Commented Feb 2, 2015 at 10:13
• @Roland: either would do, but i think the an "arbitrary but repeatable sequence" would be easier to implement. Commented Feb 2, 2015 at 10:44
• 20 MHz is your minimum frequency. What is the fastest you want? Commented Feb 2, 2015 at 11:50
• What's your ultimate goal here? That is, what do you need it for? Commented Feb 2, 2015 at 12:17

Assuming you want a pseudorandom sequence, a Linear Feedback Shift Register is an easy option. You can implement one with one or more shift registers, and a single XOR gate. Then, simply feed a clock signal into the latch pin to clock it. You can read the signal from any output pin on the shift register.

If you need a longer period than 511 bits, you can add additional shift registers.

The only complication to this is that you need to initialize the register with at least one bit set. One way to do this would be to use a shift register with output enable, tie one of the XOR gate's inputs to VCC with a pullup resistor, and use an RC circuit to ensure the output enable takes a short while to turn on after power is applied.

Here's an untested example:

simulate this circuit – Schematic created using CircuitLab

• That will not work on a 74x595, due to the extra clock delay between the shift register and the output register. And even if this were not true and this feedback worked, although the shift register is good for 32 MHz at 5 volts, adding a 74HC86 XOR will drop the worst-case frequency to about 13 MHz. Commented Feb 2, 2015 at 11:58
• @WhatRoughBeast Fair enough, I just picked a convenient shift register; there are plenty of alternatives. The extra clock cycle delay can be accounted for by moving the taps forward one position, however. I've made that adjustment, and changed the part number to 74VHC595, which appears to be plenty fast enough. Commented Feb 2, 2015 at 12:16
• Actually, if you take taps from Q7 and Q3, you'll get a sequence length of 511, rather than the 127 you've produced. Also, for what it's worth, shouldn't you have a pullup on both outputs if you've got it on one (although I don't see that you need it)? Commented Feb 2, 2015 at 12:30
• Additionally, if you specify 74VHC86, you can use 2 to make an XNOR, which will eliminate the all-zeroes lockup (although, of course, you would then have an all-ones lockup potential), and the whole thing would work to 50 MHz. Commented Feb 2, 2015 at 12:42
• @WhatRoughBeast Hah, it didn't occur to me that the latch effectively provides an extra bit, allowing a longer LFSR. I'll update the schematic. I did consider an XNOR, but it seems more robust if it's guaranteed to start in a defined state; you're right that the second input should have a pullup (or pulldown, in this case). Commented Feb 2, 2015 at 13:13

Building on the solution above, here is a three-chip version and I believe it is cheap enough for most people to build:

simulate this circuit – Schematic created using CircuitLab

The 74LVC1GU04 ("U04"), 74LVC1G04 ("C04") forms the core of the 20MHz crystal oscillator. This clocks your GAL-based LFSR. If your board have a global clock you can use that as well.

The GAL chip implements the 8-bit LFSR. By implementing the entire LFSR using one GAL chip the delay and chip count is reduced.

Check the datasheet of your PLD and you can use its internal crystal clock generator if it have one. GAL16V8 don't have one but according to some Lattice AN by using a bigger GAL like GAL22V10 (or giving up some stage bits) you can construct the clock from the PLD as well as the LFSR. (although my experiment on Atmel's ATF16V8B proves that this is a manufacturer-specific behavior)

If you ended up using a GAL, I suggest you use the DIP version and socket it, so if you found out that your random generator is compromised (can be a major security problem) you can just swap (or reprogram) the chip with a new LFSR.

• Handy, though it requires a GAL programmer. A small CPLD would be another option, and some even integrate a clock generator. Commented Feb 2, 2015 at 15:33
• Indeed. And if you have a bigger GAL like 22V10 (or if you are willing to give up some stage bits) the clock generator can also be absorbed into the GAL itself as well. 16V8 is all I have and it can be too small from time to time. However GALs in DIP package have one extra benefit as it can be socketed, so if you accidentally compromised your random generator you can change it very quickly by swapping chips. @NickJohnson Commented Feb 2, 2015 at 15:40
• wrt to security, this is by no means a cryptographic secure random number generator, do not use it for this purpose. Commented Feb 2, 2015 at 16:00
• Yes, I certainly hope the OP didn't have a security-related task in mind for this! Commented Feb 2, 2015 at 16:07