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Wikipedia’s definition of DIMM says:

Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits.

So if DRAM chips have 8 bit data width why DIMM has 64 bit data width? I mean doesn’t memory controller issue read or write request to one DRAM chip at a time? If it does what is the purpose of other 56 bits?

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  • \$\begingroup\$ If a DIMM has 9 chips per side, it should be x72 width. Of course, many systems don't use the extra 8 bits and just carry on regardless if a memory error occurs, processing incorrect data, instead of correcting it... \$\endgroup\$ – Brian Drummond Feb 2 '15 at 12:14
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doesn’t memory controller issue read or write request to one DRAM chip at a time

No, it issues the same address to all the chips at once and gets 8 bits from each of the chips (plus another 8 if it's ECC). This 64 bit chunk is then stored in a cache line.

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  • \$\begingroup\$ Now i'm so confused, let's suppose that cpu is executing "mov dword ptr [ebp-40h],0Ch" instruction,it will write 32 bit data to specific address,so these 32 bit data will be separated to 4 dram chips in DIMM module? \$\endgroup\$ – spartacus Feb 2 '15 at 11:01
  • \$\begingroup\$ More or less. The memory contents will be read out of DRAM and into cache memory. Then four bytes will be updated in the cache. Then the updated data will be written back. The memory has a 64 but days bus so it can be read or written with 64 bits on every memory clock edge, resulting in a memory bandwidth of 64 * 2 * f. \$\endgroup\$ – alex.forencich Feb 2 '15 at 11:21
  • \$\begingroup\$ @alex i'm not sure u understood me. \$\endgroup\$ – spartacus Feb 2 '15 at 12:13
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    \$\begingroup\$ "these 32 bits of data will be separated to 4 dram chips in DIMM module" - correct. \$\endgroup\$ – pjc50 Feb 2 '15 at 12:25

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