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I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and everything in between.

My project consists of a implementing in hardware, the sha256 algorithm. I have 1 pipeline of gates that is performing the algorithm. This single pipeline has about 50,000 to 75,000 gates.

Ideally I would like to fit multiple pipelines on a 350nm process. I am not sure if 350nm is small enough for this. Where can I find information about the number of gates that can be expected to be put on a 350nm process to 45nm process, of 0.063mm^2

Also, what is the performance of each process. Each step of my pipeline has delays of less than 100 pico seconds. Can I get a fast clock of 80MHz or more on 350nm?

Thank you.

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    \$\begingroup\$ You need to do more research. If you can't find the answers to these questions you probably shouldn't be doing an ASIC. Or is this a homework question? \$\endgroup\$ – Brian Carlton Jun 12 '11 at 3:08
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    \$\begingroup\$ @Brian Is this a helpful comment? \$\endgroup\$ – Alexandre H. Tremblay Jun 12 '11 at 4:34
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For basic info check out the link:

http://www.msc.rl.ac.uk/europractice/vendors/date2010_imec_foundries.pdf.

Europractice is similar organization to MOSIS with discount for European academic/research institutions. As a bonus from the link you will get a feeling what does it cost to make prototype.

For gate count per square mm rule of thumb is that each generation of process will double gate density with .18u having around 100k/mm^2 (so .13u should have around 200k/mm^2 and .25u around 50k/mm^2).

However I would never make such important decision as technology choice based on such rudimentary info. You will have to contact prototyping service (mosis/europractice) and get as detailed info as possible. As it is "digital" circuit what would be most important is as detailed info on standard cells as possible. To make things more complicated each technology will have several standard cells libraries available with different options/tradeoffs.

Also 100 picoseconds per pipeline stage sound like typo - this would translate to 10GHz clock frequency, which is out of reach even for most advanced techs. If you meant 100 nanoseconds (10MHz) I believe this is well within 350nm tech capabilities.

Side note:
I admire boldness of you endeavor and wish you success but you have to prepare for significant cost and getting some external expertise. The IC design is orders of magnitude more expensive than PCB design (both engineering and prototyping). Unless you are with academic/research facility and have prospect for sizable grant or VC backing (or VC grade money for the project) most likely you will not be able to complete it.

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    \$\begingroup\$ Thanks for all the information. I am still processing most of it. However, to address the side note. I have a price quote for 350nm from MOSIS, at 13,000$ for 240 units. This is really good. \$\endgroup\$ – Alexandre H. Tremblay Jun 10 '11 at 20:44
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The gate counts mazurnification mentions sound about right, although I seem to remember the AMS 0.35um counts being on the lower end of the trend. Maybe 18k/mm^2? I can't find the details at the moment.

Price is of course an important consideration as well - you may find that finer processes are cheaper per area. Europractice offers €720/mm^2 for flexible sized 0.35um or €16k for a fixed size 5x5mm 0.18um block. That works out at €640/mm^2 but you do lose flexibility in choosing the exact size of your device. At 100k/mm^2 you'd be able to fit about 25 of your pipelines on a block.

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Well, there is just 1 reliable way to tell: You request libs from MOSIS for the process of interest, and synthesize your schematics - now you have exact numbers :-D

Might take you just a couple of minute to figure out size with +-5% error.

You may roughly compare size of schemes by comparing area of SRAM cell - this info is usually available for all tech processes.

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