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I'm making a small board for a PIC18F26K22 microcontroller and the provided footprint in Microchip's Altium Vault is shown below:

enter image description here

I'm assuming the polygon under the IC is a GND pad, but am not 100% sure since I can't seem to find anything confirming this in the datasheet.

My concern is that the vias don't have any thermal reliefs and are untented, so isn't it likely that when the QFN chip is being soldered that the solder will get sucked through the vias as well as the GND pad possibly not getting hot enough?

EDIT: Oh, and the square pad was not named GND (which I just noticed you can see) to start with -- that was me trying to find a way to get the pad to connect to my GND net when routing the board.

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  • \$\begingroup\$ The problem that I have with this footprint is that the entire square pad should have NO solder mask on it. If that is already the way it is, then something is wrong with the way it is represented in the picture above. For that matter, it almost looks as if the chip leads don't have openings in the solder mask either. \$\endgroup\$ – Dwayne Reid Feb 5 '15 at 0:57
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    \$\begingroup\$ @DwayneReid I think purple is solder mask, red is exposed pad. \$\endgroup\$ – Nate Feb 5 '15 at 1:00
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My concern is that the vias don't have any thermal reliefs and are untented, so isn't it likely that when the QFN chip is being soldered that the solder will get sucked through the vias ...

I often see these types of pads made with untented vias. This seems to be okay because 1.) the vias are small and after plating they really don't have a lot of volume for wicking away solder; and 2.) Such a big pad will typically have an excess of solder anyway --- to avoid it you might even break up the pad into 9 smaller squares and use negative solder paste expansion to give less than 100% paste coverage on the pad. However you might want to check with your assembly house for their recommendation on how to set up this footprint for manufacturability.

... as well as the GND pad possibly not getting hot enough?

This type of package really needs to be assembled by reflow methods. Reflow generally gets the whole board, part, and solder all up to the solder melting temperature and thermal relief isn't required. You can't really get an iron onto that center pad anyway, so hand soldering isn't really a concern.

trying to find a way to get the pad to connect to my GND net when routing the board.

There are two ways to do this in Altium:

  1. Add an extra pin 0 or pin 29 to the schematic symbol and connect it to ground. Then number the center pad in the layout the same way and update the schematic from the layout.

  2. Simply click on the pad to get it's properties and change the Net property to connect it to GND (or any other net you like). I'm not sure if this could get undone the next time you sync the schematic to the layout, though.

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    \$\begingroup\$ Further note: a uC is often such a low-power part that you could probably just skip the vias. After all, the same part is also available in SOIC with no thermal pad at all. And the land pattern recommendation in the linked datasheet doesn't mention thermal vias either. But you may want to do some thermal modeling before you go there. \$\endgroup\$ – The Photon Feb 5 '15 at 5:47
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That central pad is for thermal management. Putting thermal reliefs would be unnecessary, since nothing is soldered to it, and counterproductive, since the cutouts would impede heat flow to the vias.

Since the thermal conductivity of solder is about 12% that of copper, I doubt that it matters a whole lot, and I doubt that the recommended via pattern even assumes any solder at all.

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  • \$\begingroup\$ Wait, you're saying the IC isn't connected to the pad with solder, and that it just sits on top? Wouldn't that result in a very poor connection and thus poor heat transfer? \$\endgroup\$ – Nate Feb 5 '15 at 1:27
  • \$\begingroup\$ No it is soldered to the pad. \$\endgroup\$ – Some Hardware Guy Feb 5 '15 at 1:40
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This is a good reference for QFN reflow and layout:

http://www.ti.com/lit/an/sloa122/sloa122.pdf

It has a whole section about vias on thermal pads. It says:

The thermal vias should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole. Place a ring of exposed copper (0,05 mm wide) around the vias at the bottom of the copper plane.

It also has this to say about solder loss and protrusions:

If thin PCBs or vias larger than 0,3 mm are used, designers may use only external vias to prevent solder loss and protrusions

Solder loss and protrusions result when excessive solder flowed through internal vias during reflow. These usually happen when incorrect internal vias sizes and stencil openings are used. Solder loss results in voiding and severely affects thermal conductivity. Designers are encouraged to x-ray their reflowed boards to verify that at least 50% of thermal pad area is soldered (less than 50% voiding) when using 0,127-mm thick stencils. Protrusions might cause misalignment in stencil on the reverse side of the PCB

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If it were me I'd be planning to nonconductive fill those holes and then plate flat. Of course I'd double check the part datasheet :).

I should add that in a qfn package which I assume that is? The purpose of that pad is to conduct heat out of the part so you don't want to counter act that with thermal relief.

Your assembler should be able to handle putting it down.

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From the way this is drawn, red is copper and purple is the negative solder-mask (i.e. where there isn't a solder mask).

The central pad has a "negative" solder mask (i.e. there is exposed copper in the middle). The vias are there to provide extra heat conduction to a bottom layer of copper which is your heat sink. You DO want to solder it because plain metals touching has very poor conduction properties (this is why CPU's found in computers have thermal paste between the chip and the heat-sink, even though the paste has terrible thermal conductivity compared to the raw metals).

For obvious reasons you don't want thermal reliefs on the vias on the central pad: thermal relief is there to prevent the flow of heat into/out of the via, which defeats the purpose of a heat sink. Yes, this will make soldering harder.

Depending on how you intend to run the chip, you may or may not need extra copper on the bottom for a heat sink. I would still solder it for mechanical rigidity, but realize that there really isn't a huge heat transfer benefit without more copper to sink the excess heat to (especially since it's sandwiched between the board and the chip).

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