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I am further playing around this PMOS LDO circuit I designed and attempted to test and rate (the Edit 3 schematic, simplified by removing the protection circuit). After I dropped in a NJM4559 op amp in place of LM358 it started oscillating (previous record was none of LM324, LM358, TL084 or OPA2134 oscillated). Is this a blessing from TI? (kidding)

How to calculate this circuit, since I have one more MOSFET than what I found in TI's application notes. If it was oscillating, how to stop it from doing it?

My way of determining whether the circuit is oscillating is checking for the Moire pattern on DMM readings since it is difficult to have the LDO oscillate at the frequency (or a harmonic) of the DMM's internal clock frequency. Is this way of checking for oscillations reliable? Don't yell at me about oscilloscopes as I don't have one to start with. Donations are welcome.

Here I replicate the circuit I tested. The op amp can be any one of the following: LM324, LM358, TL084, OPA2134 or NJM4559, and the last of which oscillated. R6 is a load resistor I attach when testing and value options are 10 ohms and 1 kiloohm. Respect the part numbers as those are exactly what I used.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ The DMM scheme you propose if not good. You have no real idea of what is actually happening. And if you do set out to tweak the circuit you have no real quantitative way of determining the degree to how the tweaks improve or degrade the performance. \$\endgroup\$ – Michael Karas Feb 5 '15 at 17:45
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You just cannot add gain to the output of an op-amp (extra transistors) and expect this to not oscillate without the appropriate compensation.

Look also at the data sheet of the NJM4559 op-amp that was giving you problems. There is nothing in that data sheet that even hints at what the phase margin is. I would expect to see a graph like this: -

enter image description here

This is for a TL084 op-amp and you need to study it in detail; at low frequencies the phase difference between output and input is about 180 degrees - this is what you'd expect from an amplifier i.e. it is largely inverting. As frequency rises there is usually a mini plateau were the phase angle has shifted about 90 degrees i.e. it is behaving like an integrator.

As frequency rises further, gain drops to unity and the phase margin is about 50 degrees i.e. it's 50 degrees away from being an oscillator.

Some op-amps are a bit tighter than this and for many op-amps, the unity gain point (the highest frequency that oscillation could occur) is a lot higher. For the NJM4559 this is about 6MHz. For the TL084 it's only 3MHz.

So, wiring an op-amp with regular resistive feedback and no transistors is fine for the TL084 and maybe it is for the NJM4559 but, the data sheet doesn't give any indication that it is. I would be very mistrusting of this device given the spec that I read.

Now, adding gain into the feedback loop (the two transistors) is going to cause problems nearly every single time - you are basically shifting the unity gain point of the op-amp up (maybe 20 dB or more) and this might very well move the actual unity gain point on the graph by up to 10x in frequency. You'll probably also be degrading the phase characteristics and now you have an oscillator because the phase margin has massively fallen thru 0 degrees at unity gain.

So, then re-assess what the gain is at 0 degrees and you'll find out that it's several dB above unity = oscillator.

Lower the gain of the two transistors is a good start - put a source resistor into M1 of maybe 4k7 and reduce R2 to 4k7 - this is a start but by no means might this be the only thing you need to do.

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A DMM is a lousy way to check for oscillations. Use a proper instrument instead that is called an oscilloscope.

To prevent oscillations it is necessary to add some frequency compensation in the feedback path to overall slow down the feedback response. The circuit used may very well have to be more than just a simple low pass filter.

The compensation is primarly tuned to response time of the forward path through the circuit including the opamp gain, opamp slew rate and FET switching times. There will however be some reauirement to deal with the circuit layout and nearby coupling between wires and components.

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  • \$\begingroup\$ I don't have a 'scope so I have to work around that (or I would have fired up my 'scope already) and that is where my Moire pattern method come from. Also this is all breadboard. Your telling me how a frequency compensation can be implemented would make this a better answer. \$\endgroup\$ – Maxthon Chan Feb 5 '15 at 16:50
  • \$\begingroup\$ @MaxthonChan - How will you learn if everything has to be a cookie cutter design passed out. I gave you general guidelines. Use them. Look at changing the gain in the opamp. Look at frequency selective multipole R/C filter in feedback path. Look at possibility of eliminating circuit components by eliminating the 2N7000 N-FET, using a rail to rail opamp, driving the PFET directly with the opamp and flipping +/- into the opamp. \$\endgroup\$ – Michael Karas Feb 5 '15 at 17:39
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Since you've configured M1 to have negative gain from the OA1 output to M2's gate, you need, at the very least, to flip the op-amp inputs - feedback goes to (+), setpoint goes to (-). As it is, your circuit will always oscillate - you may merely fail to see the oscillation.

The R2 feeds the roughly 4nF of gate capacitance of M2. That produces a pole in the closed-loop response at 2kHz - M2 is within the feedback loop, after all. Since M1 will be turned on to some extent during regulation, the equivalent resistance seen by the gate will be lower. Let's be conservative and simply use R2's value, though. You need to decrease R2 by a factor of 10, to 2kOhm to get the pole up to 20kHz.

You'll also need to add a local negative feedback around OA1, to stabilize it by adding a pole well under the 20kHz pole due to R2/Cin_M2. Isolate the reference voltage from the (-) input with a 4.7k resistor. Then add a 10nF capacitor from OA1 output directly to the (-) input. This produces a pole at 3.3kHz, well under the 20kHz pole of the output circuit.

This is about as good as you're going to get it with the architecture that you chose. What really kills the performance of this circuit is the use of an open-source driver M1.

Instead, you could use a couple silicon diodes in series, bypassed by a capacitor. This would restore the bandwidth in your circuit. Of course you'd still need the pull-up resistor, but it would not influence the frequency response anymore.

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