# Unexpected dominant pole in active-RC circuit

Consider this active-RC circuit:

simulate this circuit – Schematic created using CircuitLab

it should exactly realize the RLC high-pass filter with one zero:

simulate this circuit

It realizes the same equations and so the same transfer function. This model has been used to obtain an analog, elliptic, high-pass filter with a low (about 0.01 Hz) cutoff frequency.

After a simulation (with negative resistor values, supposing that they are realizable), the active-RC transfer function seems to be the same as the RLC-prototype, but with a difference: a new and unexpected pole at a very high frequency, about 10 GHz.

After $f = 10 \ \mathrm{GHz}$, the transfer function decreases regularly at 20 dB/decade and it is no more flat as it should be.

The opamps were realized through ideal VCVS generators (Voltage-Controlled Voltage Source), with a high gain ($10^9$ at least).

If the order of the filter is increased, the pole decreases is frequency. For an eight-order circuit, it is at about 100 Hz!! And it is intolerable.

The RLC-prototype used for the 8th order circuit is

simulate this circuit

And it does not have any 100 Hz pole, despite of its active-RC realization (I don't draw it for shortness).

The simulator used is Spectre (from Cadence) and the values for the RLC prototype are taken from "A. B. Williams and F. J. Taylor, Electronic filter design, 3rd edition, McGraw-Hill, 1995" (both for the 3rd and 8th order filters).

So, are there in the topology of the active-RC some elements that could be generate such a pole? Or are there some undesired parasitics automatically inserted by that simulator?

• The continuous decrease of the function (rather than being flat) is caused, of course, by the real opamp models with an open-loop gain that goes down with rising frequencies.
– LvW
Feb 6, 2015 at 13:02
• No, the opamp have been modeled with ideal vcvs generators, with a gain of $10^9$. Feb 6, 2015 at 13:37
• Check the default setting on your simulator. It may naturally add parasitic capacitance on each node. Micro cap does this and a few fempto farads at ten gig is not ignorable Feb 6, 2015 at 14:19
• V3out is the output node of an IDEAL opamp (infinite gain, and zero r,out). Hence, this output must go down to zero for very large frequencies.
– LvW
Feb 6, 2015 at 14:26
• @BowPark, I recommend to check if a change of the ideal opamp gain alters the unwanted pole. This would help to identify the source of your problem.
– LvW
Feb 11, 2015 at 13:08