So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is temperature inversion so things get faster as they get hotter and slower when colder.
If I have a 65nm chip that has a timing problem at high temperature am I looking for a setup or a hold violation? Or could it be either because it's really just the prop delay that's affected? An explanation of how/why would be appreciated.
I've done some searching, read some articles, (tried to remember what I learned last time this was an issue) but it's still not really clear to me.