I have a question about interfacing IDT6116SA15TPG SRAM to a tri-state data bus controlled by 74LS244 tri-state buffer. I could not find an old memory like 74LS289 with separated inputs and outputs.
According to the memory datasheet, when the I/O pins are in the output state the input signals must not be applied. It seems like there is a possible situation, when memory and buffer are both in the output state for a short moment during the transition period (Read -> Write or Write -> Read).
One of the ways to solve this problem is adding a delay element (like 74LS31) and a logic gate to the circuit.
Is there a better solution (something like a special memory controller / bus buffer)?