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I have a question about interfacing IDT6116SA15TPG SRAM to a tri-state data bus controlled by 74LS244 tri-state buffer. I could not find an old memory like 74LS289 with separated inputs and outputs.

According to the memory datasheet, when the I/O pins are in the output state the input signals must not be applied. It seems like there is a possible situation, when memory and buffer are both in the output state for a short moment during the transition period (Read -> Write or Write -> Read).

One of the ways to solve this problem is adding a delay element (like 74LS31) and a logic gate to the circuit.

Is there a better solution (something like a special memory controller / bus buffer)?

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What you need to do is produce well-defined read and write cycles. In this case, I'm a little suspicious of your system design. You are aware that your RAM has 15 nsec access times, right? So it doesn't take much in the way of stray skew pulses on the order of one LSTTL gate delay to corrupt your data.

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  • \$\begingroup\$ Thank you for your answer. I know, that my RAM has 15ns access time. I worry if buffer and memory are both in output state can it cause a damage of ICs? I couldn't find any information about it. \$\endgroup\$ – conscell Feb 8 '15 at 8:54
  • \$\begingroup\$ These kind of components don't blow up when one output is accidentally shorted to ground or Vcc. You may see some additional noise on the power supply. \$\endgroup\$ – TEMLIB Apr 11 '15 at 7:47

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