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I have started learning verilog recently and i am finding it difficult to understand how should i approach it because i am doing it all by myself and not from any training institute.

The problems i am facing are :

  1. Not knowing a way to approach the learning process in the best way.
  2. Not finding examples to refer to. ........

I can mention many problems here but the most important one is that i want to learn verilog in the best possible way but to do that i do not know how should i go about. Like

  1. What all topics should i study ......

So can anyone tell me the best possible way to learn verilog and along with resources to do so (preferably online resources)

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I found the Verilog Tutorial - world of asic very helpful, to learn about the specifics of Verilog a few years ago.

Being used to imperative or object oriented programming languages like C or Java, turned out to be a major issue for me, as HDL requires a completely different approach how to think about a given problem and find a solution.

Another hard lesson to learn is about the difference between testing/simulation and synthesis. Only a subset of the language can be used in logic targeted to FPGA's or CPLD's. Verilog was initial invented to test and simulate logic circuits, only later it became common to use it for synthesis, too.

IMHO Icarus Verilog is a good compiler/simulator to start with as it focuses more on testing/simulation than on synthesis.

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