7
\$\begingroup\$

What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would be nice.

\$\endgroup\$
3
  • 3
    \$\begingroup\$ What is your budget? Standard cell or full custom? Generally this is done using very expensive proprietary tools. Some of the big names are Synopsys, Cadence, Mentor, and Magma. \$\endgroup\$
    – Andy
    Jun 11, 2011 at 20:44
  • \$\begingroup\$ what country would this be? Im interested in moving their... \$\endgroup\$
    – Dean
    Jun 11, 2011 at 22:02
  • 1
    \$\begingroup\$ What leads you to believe that you can torrent software for educational purposes in Canada? The Canadian copyright act, section 29.4 part 3 reads "the exemption from copyright infringement ... does not apply if the work ... is commercially available...", and I don't even think that the exemptions apply to the use of software: They're about its duplication on slides or whiteboards or its public performance. You should talk to a lawyer before you base a major academic work on pirated software. \$\endgroup\$ Jun 12, 2011 at 23:33

4 Answers 4

9
\$\begingroup\$

Big names in EDA software are Synopsys, Cadence, Mentor, and Magma.

Here is some of the software typically involved in a standard-cell ASIC flow:

HDL simulators read an RTL description of the design (typically written in Verilog or VHDL) and mimic the behavior of the hardware described by the RTL. Wikipedia has a list of Verilog simulators; the list notes which ones also support VHDL.

Synthesis tools read the RTL description and map it onto the cells available in your target library. The cell library is usually described in .db format, and may be provided either by your foundry or by a third-party library provider. The output of the synthesis tool may also be Verilog, but it won't have any high-level constructs, only cell instantiations and wires. This is called a netlist. Wikipedia has a list of tools.

Place and route (P&R) tools take the netlist and search for a physical implementation of that netlist. This involves placing all of the cells in two dimensions and figuring out how to route the connections between the cells. Examples are IC Compiler, Encounter, and Blast Fusion.

As a design goes through P&R there will be additional quality checks including static timing analysis (using e.g. PrimeTime), layout vs. schematic, and DRC.

\$\endgroup\$
2
  • \$\begingroup\$ Can you comment on systems like Altera's Hardcopy that use FPGA tools? \$\endgroup\$
    – drxzcl
    Jun 12, 2011 at 19:31
  • \$\begingroup\$ Hardcopy essentially wires up the FPGA cells during fabrication instead of making them configurable. This makes them 'hard' like the ASIC but without the massive NRE costs of ASIC. It's an alternative to ASIC if you do not have the volume to justify the cost of ASIC. \$\endgroup\$
    – sybreon
    Jun 26, 2011 at 13:34
7
\$\begingroup\$

Many people use expensive proprietary tools for VLSI design. Others find free software or freeware adequate and more educational:

  • Magic: an interactive editor for VLSI layouts with online DRC, released under the Berkeley open-source license. Magic tutorial. Some nifty patches to Magic.

  • Alliance: A Complete CAD System for VLSI Design, is released under the GNU General Public Licence (GPL). Lots of tools, cell libraries, etc.

  • GNU Electric (thank you, sybreon), released under the GPL

  • LASI (LAyout System for Individuals), closed-source freeware

\$\endgroup\$
2
\$\begingroup\$

If this is an academic project and if you are not constrained to use TSMC's processes, you may want to consider using a tool like GNU Electric. It is able to handle some basic custom ASIC design. Depending on the complexity of your design, it might be 'good enough' for what you need.

\$\endgroup\$
1
\$\begingroup\$

In my company, the standard procedure wil be:

  • Specification (Microsoft Visio)
  • Coding text editor (Emacs/Vim)
  • Simulator (VCS synopsys)
  • Synthesize (DC_Compiler synopsys)
  • Timing Optimize (Prime Time Synopsys)
  • Routing (IC_Compiler Synopsys)
  • Post layout checking (Calibre)

You can also need Virtuoso (Cadence) if you want to do mixed-signal or ADC,DAC..

Hope that help!

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.