What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would be nice.
Here is some of the software typically involved in a standard-cell ASIC flow:
HDL simulators read an RTL description of the design (typically written in Verilog or VHDL) and mimic the behavior of the hardware described by the RTL. Wikipedia has a list of Verilog simulators; the list notes which ones also support VHDL.
Synthesis tools read the RTL description and map it onto the cells available in your target library. The cell library is usually described in
.db format, and may be provided either by your foundry or by a third-party library provider. The output of the synthesis tool may also be Verilog, but it won't have any high-level constructs, only cell instantiations and wires. This is called a netlist. Wikipedia has a list of tools.
Place and route (P&R) tools take the netlist and search for a physical implementation of that netlist. This involves placing all of the cells in two dimensions and figuring out how to route the connections between the cells. Examples are IC Compiler, Encounter, and Blast Fusion.
Many people use expensive proprietary tools for VLSI design. Others find free software or freeware adequate and more educational:
Alliance: A Complete CAD System for VLSI Design, is released under the GNU General Public Licence (GPL). Lots of tools, cell libraries, etc.
GNU Electric (thank you, sybreon), released under the GPL
LASI (LAyout System for Individuals), closed-source freeware
If this is an academic project and if you are not constrained to use TSMC's processes, you may want to consider using a tool like GNU Electric. It is able to handle some basic custom ASIC design. Depending on the complexity of your design, it might be 'good enough' for what you need.
In my company, the standard procedure wil be:
- Specification (Microsoft Visio)
- Coding text editor (Emacs/Vim)
- Simulator (VCS synopsys)
- Synthesize (DC_Compiler synopsys)
- Timing Optimize (Prime Time Synopsys)
- Routing (IC_Compiler Synopsys)
- Post layout checking (Calibre)
You can also need Virtuoso (Cadence) if you want to do mixed-signal or ADC,DAC..
Hope that help!