# Why would a 74LS14 be used to enable another IC?

As a learning experience, I am studying a 64K 80 COLUMN expansion card for the Apple IIe. The model number is 820-0067-D for those interested.

Anyway, I'm sure the schematic is online somewhere but I just wanted to do this for fun.

The first thing I noticed, however, is that it appears the designers used a Hex Schmitt Trigger Inverter (74LS14 PC) solely to enable another IC in the circuit (Octal Bus Transceiver SN74LS245N).

So on the 74LS14, they tied Y1 to !E on the 74LS245. And, since the 74LS14 has A1 tied to Y3 and A3 isn't connected to anything, it seems to enable the 74LS245.

Why would they do this? Why not just tie the 74LS245's !E enable pin to ground?

In fact, I can't see why the Schmitt Inverter is used at all. The only other connections it has is A6 to external pin 26 on the motherboard and Y6 tied to A5 and Y5 tied to nothing.

It just seems like a waste. Do you think it was used as some type of propagation delay? If so, seems like it would only be around 50ns or so.

Here is a crude schematic that I came up with. I might just try and dig up the real schematics to make sure I'm not crazy. lol

simulate this circuit – Schematic created using CircuitLab

EDIT

Looks like I was wrong. A3 does indeed connect to Y5. Also, A2 is not floating, it is connected to GND.

It seems your circuit is incomplete or got pins mixed up. It is extremely unlikely that outputs of the 74ls14 are used with the input being open.

Using a schmitt-trigger circuit when receiving clock/enable like signals to improve noise immunity is quite sensible. As the 74ls14 is inverting, connecting two inverters in series to remove inversion is sensible and common. Thus it seems like you miss the A3 input. Finally while the delay is small, it might be sensible to make sure that the clock or enable signal arrives after some data signal or further control pins. The propagation delay through two schmitt triggers might well be enough for that.

• One of the nice things about SSI/MSI TTL ICs is that they normally have well-characterized minimum propagation delays (as well as maximum). It was common back in the days when this kind of design was being done to use gate delays to control the sequencing of data sources onto a bus, fine-tuning the enabling and disabling of different drivers to insure that they wouldn't "fight" each other, while still meeting setup and hold times on the actual data transfers. – Dave Tweed Feb 8 '15 at 16:57
• I'll check the continuity later on like I mentioned in a comment below. But, visually at least, it appeared that A3 was floating. The bottom IC (74245) is incomplete in my drawing above because I was only concerned with the !E pin. However, the top IC appears to be complete in my drawing above. Again, based on a purely un-scientific visual inspection. A small propagation delay would make sense to me. But, being such a n00b, I am a little confused on how/what the noise immunity is. Do you have more info on what that is and how it affects circuits? – cbmeeks Feb 9 '15 at 16:32
• In an ideal circuit, a signal that changes from high to low goes low at all inputs pins exactly at the point in time the output gets driven low. In a real circuit, pulling a signal low means discharging its capacitance, which is hindered by the inductance of the traces. So even if one manages to do a hard step at the output creating a signal, the step will arrive distorted at input pins (mostly the step will be washed out), and in case of splitting traces without proper termination, you can even get reflections and get very funny curve shapes from high to low or low to high... – Michael Karcher Feb 9 '15 at 23:34
• ...and if you add noise (some random variation of the voltage), the point-in-time of the detection of the edge is not that certain anymore (especially as TTL chips have a quite big "forbidden zone" between 0.8V and 2.0V, and the edge might be detected at any voltage in there), and if you are unlucky, funny shapes of an edge can be detected as three edges (fall, rise, fall). A schmitt-trigger device is made to deal especially with the false detection of multiple edges by adding hysteresis - i.e. the threshold for low-to-high is at a higher level than the threshold for high-to-low. – Michael Karcher Feb 9 '15 at 23:39
• Thank you for that explanation. I'm just recently learning a little more about hysteresis in general. But you're also saying, that an ideal circuit should also never have floating pins? Granted, I'm sure many a product has been made floating but it isn't ideal. – cbmeeks Feb 10 '15 at 18:29

Your schematic is incomplete. There is at least one connection you've missed, which is Y5. I suspect it connects to A3. You might want to check continuity.

In any event, the external Pin 26 provides a signal which is used to let the card act as an auxiliary memory. The input is active low, and the LS245 is active low, so using 4 LS14 gates will provide signal buffering as well as a reasonable delay (nominally about 60 nsec). Since this is board-level enable line, I'd guess that the delay is irrelevant. More likely, I think, is that using 4 gates rather than the 2 which would make sense when seen from the point of view of buffering, may well be driven by pcb routing considerations.

• A good idea on checking continuity. I was only checking visually with a magnifying glass. I was pretty sure Y5 and A3 went nowhere but I will do a continuity check later and see. So you're saying that you think it's used for signal buffering? And, because of the way the Apple IIe was designed (routed), the extra delay might have been needed? (4 instead of 2). – cbmeeks Feb 9 '15 at 16:24
• A trace from Y5 to A3 will almost certainly be entirely under the IC on the top layer, so you can't see it. And when I say routing, I mean physical routing, actually laying out the traces so that you can connect pin A to pin B. And I doubt the delay is important, but I don't know enough about the motherboard function to be sure. – WhatRoughBeast Feb 9 '15 at 16:50
• That was spot on. Yes, Y5 is connected to A3. I checked it with a continuity tester and sure enough, they are connected. – cbmeeks Feb 11 '15 at 2:30

TTL floating inputs inputs default high, so A3 high will make Y3 and A1 low, which will make Y1 permanently high, permanently disabling the '245.

There's obviously something happening at A3 that you missed, so you need to backtrack and reverse-engineer a little deeper.

• Ah, I guess I should check my datasheet but I setup a 74HC14 on a breadboard. I connected VCC/GND, of course, but also connected A1 to Y3 and then probed Y1 which was 0.8V IIRC. Which I assumed would be LOW. The other pins (floating) came up around 0.7-0.8V as well. Leading me to assume floating pins were default LOW. – cbmeeks Feb 9 '15 at 16:28
• On 74HCxxx (High-speed CMOS), unconnected inputs are undefined, and can provide either level, or even pick up radio signals or signals from neighbouring traces. 74LSxxx on the other hand is a bipolar technology (Low-power Schotkey TTL) which defaults to input high. The answer by EM Fields is limited TTL chips (74xx, 74Sxx, 74LSxx, 74ALSxx, 74Fxx, 74Lxx), not about any chip with a pinout compatible to well known TTL ICs (like 74HC, 74AHC, ...). – Michael Karcher Feb 9 '15 at 17:43
• Your question's illustration showed 74LS as the logic family you were using, in which inputs default to high if they're left floating. As Michael Karcher noted, CMOS inputs - which the 74HC family uses - left disconnected can float anywhere, so if they're not used they must be connected to a voltage either higher than Vih or lower than Vil, Vcc or GND usually being appropriate. – EM Fields Feb 9 '15 at 18:45
• Ah, thank you both. I didn't know that about HC components. I knew that my HC wasn't exactly like the LS used on the actual circuit but knowing that difference makes sense. Also shows me I can't always assume any results without knowing ALL of the parameters. lol – cbmeeks Feb 10 '15 at 18:33