# D flip flop with asynchronous level triggered reset

My code :

always @ ( posedge clock, posedge rst)
begin
if(rst) q = 1'b0 ;
else q = d ;
end


Waveform :

Error :

Between 100 and 150 ns, the output followed the d input although there was no clock edge. In other words, it behaved like a latch.

I wanted to make a positive edge triggered d flip flop with asynchronous positive level triggered reset, which I succeeded after examining the reference link above.

Prior to this, I was using the code given above. As you can see, the only difference is that I have used blocking assignment while the reference uses non blocking assignment.

Now I know that non blocking assignment schedules the values in contrast to blocking assignment. However I am not able to understand how is this affecting my design ? In other words, can someone explain step by step or in little detail why changing non blocking to blocking is resulting in incorrect design.

Additionally, I also tried this code :

always @ ( posedge clock, rst)
begin
if(rst) q = 1'b0 ;
else q = d ;
end


which also resulted in erroneous design. But why, I wasnt able to understand.

Thank you.

• Can you share the test-bench and tell us what simulator and version you are using. If your design is only one flip-flop, blocking vs non-blocking assignment shouldn't be an issue. My guess is there is a glitch on clock or rst, or bizarre simulator behavior. – Greg Feb 10 '15 at 0:28
• @Greg . You were right. I use modelsim student version. Today I reinstalled the simulator after your comment. Seems like it now works as expected. Just one last thing, can you explain the last block of code ; it sure doesnt result in FF but why ? – Plutonium smuggler Feb 10 '15 at 12:39

The best answer for blocking vs non-blocking flip-flops assignment is already answered on Stack Overflow here. That answer also references to a paper by Cliff Cummings, here.

Now, the code for your second attempt will always result in with the behavior shown in the waveform, even with non-blocking assignments:

always @(posedge clock, rst)
begin
if (rst) q <= 1'b0 ;
else     q <= d ;
end


This is because the sensitivity list for signal rst is incorrect. The posedge keyword only applies to the signal immediately right of the keyword and not the following signals after the comma. @(posedge clock, rst) is equivalent to @(posedge clock, posedge rst, negedge rst). The else condition will be evaluated on the falling edged of rst, which is not desired.

A good linting, synthesizer, or LEC (logical equivalently check) tool should flag the dual edge trigger on rst as an issue; possible as a warning.

• @ is trigger by events: edge triggered, value change, or triggered event type (not synthesizable) within the sensitivity list. posedge rst with if (rst) tells the synthesizer to use a D-flip-flip with an active high asynchronous reset. Asynchronous is for events outside of the synchronous domain. For a active low reset async reset you need negedge rst with if (!rst). For sync reset, remove rst from the sensitivity list. Behavior will be correct in simulation. You may run into trouble on FPGAs with limited number of flops with async set/rst, but that should get errors/warnings – Greg Feb 10 '15 at 20:08