My code :
always @ ( posedge clock, posedge rst) begin if(rst) q = 1'b0 ; else q = d ; end
Between 100 and 150 ns, the output followed the d input although there was no clock edge. In other words, it behaved like a latch.
I wanted to make a positive edge triggered d flip flop with asynchronous positive level triggered reset, which I succeeded after examining the reference link above.
Prior to this, I was using the code given above. As you can see, the only difference is that I have used blocking assignment while the reference uses non blocking assignment.
Now I know that non blocking assignment schedules the values in contrast to blocking assignment. However I am not able to understand how is this affecting my design ? In other words, can someone explain step by step or in little detail why changing non blocking to blocking is resulting in incorrect design.
Additionally, I also tried this code :
always @ ( posedge clock, rst) begin if(rst) q = 1'b0 ; else q = d ; end
which also resulted in erroneous design. But why, I wasnt able to understand.