enter image description here

I am trying to create a bloc with Xilinx system generator to detect the maximum of a sine wave. I used the strategy that:

$$ x(n-1)-x(n-2)>0$$


$$ x(n)-x(n-1)<0 $$

but I didn't find the maximum. The result is wrong, as shown in the image below:

What am I doing wrong? How can I detect the signal maximum?

enter image description here

  • 1
    \$\begingroup\$ Can you scale your graph so that it's clear when the digital signal is high and when its low? \$\endgroup\$ – The Photon Feb 9 '15 at 17:33
  • \$\begingroup\$ How fast are you sampling and what is the frequency of the sine? \$\endgroup\$ – Eugene Sh. Feb 9 '15 at 17:43

Assuming I guessed right about which edges in your graph are rising edges and which are falling edges, it looks like your solution has found the maximum, but it's output is delayed by two cycles from when the maximum occurred. You should expect this delay because the new value of y (your output variable) can only be determined once x(n-2), x(n-1), and x(n) have all been produced. Therefore, y only responds to the maximum in cycle n+1.

You could get the response in cycle n if you used only combinatorial logic to compare x(n) with the prior values, and didn't wait for a flip-flop to capture the result.

P.S.: You'll also have a problem if your sampling happens to produce two exactly equal samples (to the resolution of your ADC) straddling the maximum point.

  • \$\begingroup\$ I used the bloc sine wave and I didn't change the frequence ,the proprieties is (1= frequence/second) and (sample = 0), I changed parametre but the signal became a constant and no a sinusoid \$\endgroup\$ – Marie Feb 9 '15 at 17:53
  • \$\begingroup\$ If you either increase the sample rate or decrease the frequency of the input, the output delay will be a smaller fraction of a period. But I don't use X.S.G. so I don't know how to do those things. \$\endgroup\$ – The Photon Feb 9 '15 at 17:57
  • \$\begingroup\$ Thanks for your reply ,I used f =60 and sample= 360 but the output is 0 all the time , can you suggest value to test this bocs \$\endgroup\$ – Marie Feb 9 '15 at 18:02
  • \$\begingroup\$ I don't use X.S.G., so I don't know what those values mean. If your signal frequency is 60 Hz, and you want the output delay less than 1/100 cycle, you need to use a sampling rate of at least 12k samples/sec. \$\endgroup\$ – The Photon Feb 9 '15 at 18:58
  • \$\begingroup\$ th sine is from simulink Library and not xilinx system generator \$\endgroup\$ – Marie Feb 9 '15 at 20:33

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