3
\$\begingroup\$

Similiar to the question What are the advantages and disadvantages of thinner PCB thickness (<1.6 mm)?, but going the other way.

If we look at the picture in the previous question's answer, we have the following

enter image description here

If I increase the dielectric/prepreg spacing to something much higher, say 0.1 in, are there any negative effects ?

Will this stackup perform just as well as if the dielectric/prepreg was 0.04 in with all other things equal ?

\$\endgroup\$
  • \$\begingroup\$ Are you asking about disadvantages other than the ones mentioned in the question you're citing? \$\endgroup\$ – Dave Tweed Feb 9 '15 at 23:59
  • \$\begingroup\$ I can't comment on the signal integrity question, but I can say that I have worked with 2-layer PCB's that were ~0.250 inch (~6mm) thick. They each had 5 large, many-pin connectors that mated to some automated testing machines. They might be mounted/unmounted several times a day by temp labor... \$\endgroup\$ – AaronD Feb 10 '15 at 0:01
  • \$\begingroup\$ @DaveTweed the disadvantages I read from the previous question were more mechanical oriented. None of which really touched from a SI perspective. \$\endgroup\$ – efox29 Feb 10 '15 at 0:06
3
\$\begingroup\$

The increased spacing in the middle lowers the effectiveness of plane capacitance which depending on your application may or may not be useful to you.

The decreased spacing from signal to plane will let you use thinner traces to achieve similar impedances, while reducing the effect of cross talk between signals (assuming the same trace to trace spacing in each Stackup). The closer to the plane the more contained your field will be and you should also see less radiation. You can see this effect nicely in say hyperlynx if you have access to it ( or others they just draw nice field lines)

Given the choice I would go with thin dielectric for outer layers usually 3-5 mil for me, vs thinner spacing between the inner layers.

Editing to add: I'm just talking SI/PI here. Increasing the inner core thickness to 100 mil will also increase the length of your vias, which increases their inductance and reduces their effectiveness at pulling current out of your planes as frequency goes up. So it has the effect of increasing the inductance of decoupling capacitors (assuming you're using vias to connect your caps to planes), as well as your package to plane connection. Basically the increased distance with all other things being equal will have worse power integrity. It doesn't mean you can't do it but that's an effect and if it's a concern you'd have to understand the consequences before increasing the thickness. You could mitigate it for example by adding more vias.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.