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First post here, so sorry for mistakes or inappropriate posting.

This was one of the tasks in a digital logic exam I failed today. The exact request was "Design a synchronous frequency divider to 13(state diagram, truth table, electronic scheme). Draw the signal/time diagram for the outputs Q."

As I understood from the course, frequencies can only be divided by powers of two (2,4,8,16 etc). Is this divider even possible at all? I had no idea even where to start.

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  • \$\begingroup\$ Use divider with mod number < 2^n ie you can reset your counter at 13. \$\endgroup\$ – Plutonium smuggler Feb 10 '15 at 19:47
  • \$\begingroup\$ What is the range of the frequencies you have to support? If it's not very high, you can use a counter with the 13th output connected to the reset pin. You'll also need a flip-flop to have the high&low state with the same length. \$\endgroup\$ – fceconel Feb 11 '15 at 13:05
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Since you've already failed the exam, I feel a little bit better about helping you with homework.

You can multiply and divide clocks by any number you want. It just happens to be super easy to divide by powers of 2 and so that's what they taught you first.

  • To divide by a different integer, count so many cycles and reset.
  • To multiply, use a PLL* with a divider in the feedback.
  • To multiply or divide by non-integers, use a combination of integer multiplication and division.

*PLL=Phase Locked Loop. It's basically a variable clock that is constantly adjusted to match a different clock. Mess with it before matching, and you can make it an exact variation of the reference.

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  • \$\begingroup\$ If one has a somewhat symmetric clock, dividing by a multiple of 1/2 (e.g. dividing by 1.5) doesn't require a PLL, but instead requires a mix of combinatorial and sequential logic. The output won't be symmetric, and if the original clock isn't symmetric, the output will be lop-sided, but if the original is close to symmetric the output will be close to periodic. \$\endgroup\$ – supercat Feb 10 '15 at 21:14
  • \$\begingroup\$ @supercat Yeah, that works too, but it imposes an extra requirement on the input clock. If that's not a problem, then it's a good tool to have. The PLL almost always works as long as there's an edge in there somewhere, but it's a bit more expensive. \$\endgroup\$ – AaronD Feb 10 '15 at 21:22
  • \$\begingroup\$ A PLL requires that the original clock be stable for awhile before the PLL output will be usable. A divide-by-1.5 can start and stop on a dime. \$\endgroup\$ – supercat Feb 10 '15 at 21:32
  • \$\begingroup\$ True. It'll probably adjust itself way out of whack before it figures out that the input has stopped, and it has to figure itself out again when it restarts, but for everything I've done, the startup time is negligible and I really don't care at all about shutdown. Your mileage may vary. \$\endgroup\$ – AaronD Feb 10 '15 at 21:58
  • \$\begingroup\$ I'm not sure a PLL is what I had to use as we've never studied such a thing in the courses. The professor covered mainly logic gates, mux/demux and flip-flops. \$\endgroup\$ – Danesan Dragos Feb 11 '15 at 18:28
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I'll give you a few hints, then as you fill in the details, I'll add to this answer.

You should know how to use J-K flip-flops. If you don't know what they are or what makes them applicable for this, you need to do some studying.

We are going to use J-K flip-flops because you specified that you want a synchronous counter. That means that all of the flip-flops are clocked at the same time. What controls when the flip-flop changes state is the level on the J & K pins.

Give this some thought and modify your question with your first attempt at this.

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  • \$\begingroup\$ I sort of thought JK's are what I had to use because I saw such examples in the lectures, but all of them divided by powers of two. There was even a paragraph explicitly saying that "in general, a binary counter provides signals having frequencies obtained by dividing the clock fequency by 2^n". Or am I reading the wrong example? \$\endgroup\$ – Danesan Dragos Feb 11 '15 at 18:26
  • \$\begingroup\$ In general, yes, but if you look at the bit pattern, you'll see that the 2^n points are easy special cases of something more general. That test question was supposed to make you think and not blindly apply some canned procedure. \$\endgroup\$ – AaronD Feb 11 '15 at 19:44
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One important thing to know is, that 2^0 is a power of two as well. This will be the key to odd numbers like 3,5...13. As an exercise, write down numbers using a binary notation. Further: connect D-flip-flops in a serial order and draw a diagram, showing input and output signals. With a breadboard or a simulator you can use the CD4013, it contains 2x D-FF. google 'datasheet cd4013' and you will find some helpfull and practical information. The "General Description" of the datasheet says: "The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock pulse." Imagine what will happen, when you connect the inverted Q-output to D. The 4013 is a fun toy to play around with! Do not forget to use proper resistors when you go for a breadboard and LED's... All the best!

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  • \$\begingroup\$ I thought of the fact that 2^0=1, but wouldn't that just mean that the frequency is divided by 1? Which means it will stay the same? It was a theoretical exam, so getting the actual components on a breadboard would be nice experience, but not that much help. \$\endgroup\$ – Danesan Dragos Feb 11 '15 at 18:21

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