I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual.

I am using the fifo generator version 9.2 (manual ) to generate a fifo.

I would like to insert the timing constraints which are suggested on page 151:

Add the following constraint to your design – this constraint sets a timing constraint to
the synchronization logic by requiring a ma
ximum set of delays. The maximum delays
used is defined by 2x of the slower clock period.
wr_pntr_gc<0> MAXDELAY = 12 ns;
wr_pntr_gc<1> MAXDELAY = 12 ns;

If I insert these contraints I get the error:

NET not found

I expected a spelling error, so I searched for this net with PlanAhead, but I could not find a net with this name. I found a primitive which has a similar name ( rd_pntr_gc_9) but no net.

My question is now, what am I doing wrong? Why are the nets not existing? Which nets could I use instead to apply the constraints.

I am using ISE 14.2 and a ml605 board with a Virtex 6 FPGA.

Thank you and best regards


tl;dr I want to insert the suggested timing contraints for a fifo from the manual, but I cannot find the nets which are suggested.

p.s. I have seen the answer record AR# 43210, the nets which are described there are also not existing in my design.

Edit: XST option -keep_hierarchy is set to Yes

  • \$\begingroup\$ What is the XST option for keep_hierarchy? It should be soft or yes, so the netlist is not flattened. \$\endgroup\$ – Paebbels Feb 11 '15 at 11:19
  • \$\begingroup\$ keep_hierarchy was set to Yes \$\endgroup\$ – Simone Feb 11 '15 at 12:19

I to had this issue with ISE14.7 i was able to get the TIG by changing the NET to INST but the MAXDELAY can only be on a net. The output net from that instance is not (from PlanAhead) the same net name as the instance.

  • \$\begingroup\$ Could you add a little bit more detail to your answer? \$\endgroup\$ – jose.angel.jimenez Dec 18 '15 at 8:06

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