# What is the set in D FF?

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment by 1. There are 3 outputs count(0), count(1) and count(2) where count(0) is the lsb.

But I'm not sure how can I handle the set in D-type flip-flops. I have illustrate as follows but you can find there is set port in DFF. So How can I make set in verilog? I'm not sure is this meaning reset? if yes, what if set is 1, is meaning negative reset? or positive reset?

How do I modify as above rule (the input is an increment signal that when set to 1 will allow the counter to increment by 1)? Am I interpreting it right or wrong?

UPDATE:

Is this the same thing?

always @ (posedge clk or negedge reset )
if(set)
begin
Q<=1'b1;
end


UPDATE:

   wire q0;
wire q1;
wire q1_i = (q0 ^ q1);
wire q2;
wire q2_i = (q2 ^ (q0 & q1));

dar u_dar1 ( ~q0 , clk , reset_n, q0);
dar u_dar2 ( q1_i , clk , reset_n, q1);
dar u_dar3 ( q2_i , clk , reset_n, q2);

wire [2:0] rere = {q2,q1,q0};

module dar  (
data  , // Data Input
clk    , // Clock Input
reset , // Reset input
q         // Q output
);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end  else begin
q <= data;
end

endmodule

• In D FF, if you put 1 on D (while CLK=1), then you are setting it, if you put 0 on D (while CLK=1), you reset it (clear) Feb 11 '15 at 14:12
• @Triak Thanks Dir, I have just updated it. would you please check it. if you can illustrate, please modify it. Feb 11 '15 at 14:17
• @Morgan Would you please some advice to me? Feb 11 '15 at 14:54
• @Carter, for some reason I have chosen the name 'pre_randomize' on this site but it is me morgan from SO. Feb 11 '15 at 15:08
• @pre_randomize, Sir I don't know from where to start to make above function. Feb 11 '15 at 15:11

## 4 Answers

The Set-Reset-flip-flop is not often used, the syntax tends to look 'wrong' to those not used to seeing it. You can actually have 3 edge sensitive signals in the sensitivity list: Active low reset has priority.

always @(posedge clk or negedge reset or posedge set ) begin
if (~reset) begin
Q<=1'b0;
end
else if (set) begin
Q<=1'b1;
end
else begin
Q <= D;
end
end


For a counter which will increment by 1 when enabled, there is no d=need for set_reset_flip-flops.

A clean RTL version could just be:

always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
Q <= 'b0;
end
else begin
if (increment) begin
Q <= Q + 1'b1;
end
end
end


Where increment is a synchronous signal. This has 3 flip-flops Q feeding into a Half adder with a single bit 1 as the other operand. You only need a half adder to increment by 1.

• Wow, it's very clear the set Feb 11 '15 at 15:14
• But. Sir, should I have to need to the set port control to intialization? There is no reset, then I have only set control to reset. Feb 11 '15 at 15:15
• I will roll this in to answer later but for now; No at time 0 assume there is no power to circuit. all signals get initialised as we power up, we have active low reset meaning 0 (GND) puts the flip-flop into reset. This has priority and no other signals can effect output while reset is active. For ASIC the reset is normally controlled from a Power on Reset block that releases the reset after 2 full clock periods this ensures all other signal can be initialised properly before the reset is released. Feb 11 '15 at 15:18
• As this rule, (The input is an increment signal that when set to 1 will allow the counter to increment by 1.) should I add inverter at rst port?. Feb 11 '15 at 15:19
• @Carter I had already updated question to include an incrementing counter, see end of answer. If you are still stuck I would suggest a new question clearly stating the current problem. Feb 11 '15 at 18:58

SET forces the output (Q) high and the inverse output low. CLR "clears" the flip-flop, meaning the output is forced low and the inverse output high. The SET and CLR inputs are asynchronous to the clock, meaning they work at any time, not just on a clock edge as the D input does.

• Thanks Sir, then, is this same thing as follows? always @(posedge clk or negedge reset_n) { if(!reset_n) {D=<=0)? Feb 11 '15 at 14:21
• As you said, if set = 1 then Q is 0,set = 0 then Q is 1. And if CLR = 0 then Q is 1, CLR = 1 then Q is 0. then is this just the same function between CLR and set? Feb 11 '15 at 14:49
• @Carter: No, when SET is high, Q is forced high. Feb 11 '15 at 14:55
• Thanks, But How can I initialization to above circuit? Feb 11 '15 at 14:58
• What is the first flip-flop's output value? while clocking. Feb 11 '15 at 15:01

Set and clear are asynchronous in a D-flipflop. They override the inputs of the cross-connected output gates, so depending on whether you use NAND gates or NOR gates you AND or OR Set and Clr with the inputs of these gates.

• Thanks Sir, did you mean that I don't need reset? But How do I handle the set like this? The input is an increment signal that when set to 1 will alow the counter to increment by 1. it rule is need to control the set signal. Feb 11 '15 at 14:19
• You don't need the reset, and you don't need set either, to make a D-flipflop work. In discrete versions, when available they're usually active-low, and then you connect them to Vcc if you don't need them. Feb 11 '15 at 14:42
• But How can I set to 1? Should I need something else to do like this? (The input is an increment signal that when set to 1 will alow the counter to increment by 1) ? I mean that there are no any initial value. Feb 11 '15 at 14:45

Some flip flops can only change state when the clock input changes state. Some change state in response to a clock input but have an additional input, called "asynchronous reset", which can force them to go low regardless of what the clock is doing. A few have an input, called "asynchronous set", which can force them to go high regardless of what the clock is doing.

In a flop with genuine asynchronous set/reset capabilities, driving the "asynchronous set" input when the "asynchronous reset" pin will unconditionally drive the output high regardless of what the clock is doing or has done previously (even if a glitch on the clock had left the output in a metastable ["confused"] state). Likewise driving "asynchronous reset" will make the output go unconditionally low. Importantly, in cases where having one input switch cleanly before the other would yield the same output as having it switch cleanly after, having them switch simultaneously will yield that same result, and the output will never change state even momentarily except in cases where it is specified to do so.

It is possible to use "plain" flip flops, or async-reset flip flops along with combinatorial logic to "synthesize" an async-set-reset flip flop whose VHDL or Verilog behavioral description will match that of a real one, but synthetic async-set-reset flip flops almost always differ from real ones in ways that may be important, but which those languages can't really express. For example in the following circuit (the right half represents the synthesized async set/reset flip flop, and the left half can generate test signals in simulation)

simulate this circuit – Schematic created using CircuitLab

the output will only switch in response to a proper input stimulus (clicking on the schematic and selecting "simulate/transient analysis" should generate a timing plot), but it will be observed that there are three flip flops which will each change state in response to an input stimulus that should cause the output to change state, but the simultaneous arrival of two signals which should both cause the output to change state may in fact result in the output state changing state twice quickly (erroneously returning to its previous state).