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Looking for the simple way to protect output pin of microcontroller with VCC 1.8V - 3.3V, from VPP 6.5V that will be applied sometimes, only during high state (1.8V - 3.3V) on pin output. Easiest way will be to put few kohm resistor between, but this is not possible because of high speed on PIO (6 MHz). Driving current on micro pin is few mA. I guess that isolation can be done with some fast low drop diode like MBR0450.

All things that I can find by google are related to ESD, and 3.3V / 5V glue logic.

Regards, Josh

Edit:

Just for further clarification. This is only output pin / signal, and 6.5 V is applied to line by FET under same micro control. Changing 1.8V / 3.3V to 6.5V must be continuous (logic hi) without glitches. Only solution that I know (lower frequency) is...

enter image description here

but instead of 1G is direct pin connection. However, micro is connected over flat / ribbon cables to other side and with 150R and 1 meter cable length with 6 MHz signal is working just fine. Don't want to be forced to reduce cable length because of VCC/VPP interface, so looking for some better diode than LL103A, or some other design, whatever. Maybe somebody know why on picture 2k7 is used, and not for example 10k. On other side signal is grounded over 50k resistor.

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  • \$\begingroup\$ Can you predict when it will happen and switch a transistor? \$\endgroup\$ – AaronD Feb 11 '15 at 20:26
  • \$\begingroup\$ Since it is output only, try using diode (schottky maybe). \$\endgroup\$ – Triak Feb 11 '15 at 20:27
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There's a very clean technique for level shifting that you could use here. You place a low-voltage FET in line with your I/O signal from the processor (Drain to the processor and source to the outside world), and drive the gate with the highest voltage you can stand-off -- in your case you'd tie your VDD(3.3V) supply line to the gate.

The FET will stay on for any ground current (since the g-s voltage is high), and would be less and less conductive as the source voltage approached the gate, until, once the source voltage goes above the gate: then it turns off. Note this allows logic levels to go both directions as long as each side has a pull-up to their respective regions supply voltage.

Here's a link of how someone else did something similar, and a drawing of how to do it.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ This one is new to me, and probably will be just fine for my interface. I will search for low voltage FET (1.8V - 3.3V) with shortest turn on/off delay time. \$\endgroup\$ – josh Feb 20 '15 at 8:45
  • \$\begingroup\$ Yes, and I've tried this with 'standard' FETs and it doesn't work so good - PMF370XN from NXP has a really low threshold, so I'm looking to try it on my next 5V or 3.3V level-shifter implementation. \$\endgroup\$ – AccelMotion Feb 20 '15 at 15:57

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