This is the first schematic I have made that was not a simple LED. I want to know if it seems good before I go and build it (and buy the parts). Here is the schematic:

enter image description here

Here are a few of my concerns:

1.) Are there any silly shorts that I should address?

2.) Did I connect the 556 correctly (In monostable mode, don't worry about the resistor and capacitor values too much)

3.) Are there any pullup or pulldown resistors I am missing?

4.) Did I make the h - bridge correctly (I will change the transistors as I need more current. I have not decided on a motor yet).

It is essentially a tennis ball machine (using logic gates because arduino is too easy :P). There are three lasers and photo transistors and a button. The only important thing really is that when the laser is tripped, the signal should go low (unless I got this backwards) and when the button is pressed, it should go high.

One last thing - pretend that voltage regulator you see is a UA7805 (I couldn't find it in Eagle).



  • \$\begingroup\$ By the way, I know I should probably use a Schmitt trigger, but don't worry about that yet. I will add that later if I REALLY need it. \$\endgroup\$ – electricviolin Feb 12 '15 at 2:44
  • \$\begingroup\$ I see there have been some improvements to the schematic. See the newest answer below for updated recommendations. \$\endgroup\$ – Nedd Feb 13 '15 at 17:22

Are there any silly shorts that I should address?

Yes. For example, all of the inputs to your logic (IC2 and IC3) are connected to the same node, the one connected to the collector of Q7. I'm guessing that this isn't what you really wanted, but of course, without a functional description of the board, it's impossible to be sure.

  • \$\begingroup\$ Thanks for the response. That is what I wanted because it is a two part mechanism. When only one laser is tripped (the one labeled "Slot ready"), the machine dispenses the next ball. This is the point at which the second laser is tripped, but both lasers have to be tripped at the same time (which is why I used a NAND gate) at which point the next action begins. \$\endgroup\$ – electricviolin Feb 12 '15 at 3:01
  • \$\begingroup\$ What is being pointed out is that all of the signals coming from the photo transistors are on the wrong side of the pull up resistors (you presently have them all on the power line side). The detection signal should come from the collector pin side. \$\endgroup\$ – Nedd Feb 12 '15 at 3:09
  • \$\begingroup\$ Hmm... okay. I will fix that and reupload tomorrow. I think @Peter was saying the same thing. \$\endgroup\$ – electricviolin Feb 12 '15 at 4:01
  • \$\begingroup\$ The two pots R19 and R20 can short the +12 volts to ground (or more likely destroy the pots), depending on their setting. You have specified single gates - I suggest you use "normal" multi-gate parts that are available in standard DIP packages - then you can build and debug the thing on a plastic breadboard. You have two transistors in series switching the +5 volts - it would be better to use a single transistor there, and use a NOR gate to combine the two signals controlling those transistors. \$\endgroup\$ – Peter Bennett Feb 12 '15 at 4:52
  • \$\begingroup\$ @Peter, as shown the action from the two Q outputs to the two transistors is actually a NAND function enabling the supply output. (Both Q's need to be hi to enable both PNP transistors, - A NOR would give a lo if any Q is hi.) \$\endgroup\$ – Nedd Feb 12 '15 at 5:08

This should really be a comment, but I need to show a schematic.

All places where a transistor (or photo-transistor) drives a logic input should be something like this:


simulate this circuit – Schematic created using CircuitLab

You don't need the resistors you show between the transistor collectors and the gate input, but you do need pull-up resistors to ensure that the gate input is high when the transistor is off.

For the PNP transistors, you need a similar circuit, but with the resistors going to ground, and the emitters to a positive supply.

It appears that you want the photo-transistors at the bottom to provide inputs to some gates, but the gate inputs are connected to the positive rail, not to the phototransistor collectors.

There is no indication of any outputs on the schematic - you may know where they are, but the rest of us have to make wild guesses.

  • \$\begingroup\$ I see what you are saying. That was actually one of my concerns (if the transistors will work with the logic gates). I will add the pullups for the photo transistors and get rid of the other resistor I put there. Also, which PNPs are you referring to? I will upload a new schematic tomorrow and let you know once I update it. \$\endgroup\$ – electricviolin Feb 12 '15 at 3:32
  • \$\begingroup\$ Q5 is the PNP transistor. \$\endgroup\$ – Peter Bennett Feb 12 '15 at 3:36

For R19 you should have the center tap pin going to the + motor, then ground the - motor pin separately. The other R19 pin can be connected to the center tap (or just left open). Your original connection setup could have shorted the +12 to ground. Note that using a resistor in series with a motor like this will not be very efficient. If the motor is a high power type you may need a high power variable resistor.


simulate this circuit – Schematic created using CircuitLab

For R20 I would think you want the variable center tap pin going to the THR-DIS inputs, then the other pin of R20 can be connected to the center tap (or just left open). Another small resistor (Rm, maybe 1/2 value of R20) should be included to prevent shorting these pins directly to +12. This setup would give you variable timing control of IC9B, as I assume you desire. As with R19 your original setup you could have shorted the +12 to ground.


simulate this circuit

The two 556 Q outputs, inverters IC11-IC12, and Q6-Q7, form a NAND gate action that turns on the + supply voltage. You could replace this group with just one NAND gate and one transistor. Using only one transistor will reduce voltage drop in the + supply line. For this transistor (or if you keep the same arrangement on both) you still need a small value resistor in line with the transistor's base to limit the base current. Depending on the motor current requirements you may need a higher power transistor here. (You could use a P-channel Mosfet here instead of a PNP).


simulate this circuit


A few things to improve on for the updated Schematic:

1) The LM556 should not have +12 inputs (eg.: RC and Reset pins) while being powered from +5v, possible burn out. Much better to keep all inputs and power at the same supply level.

2) The four switching transistors (Q5,6, T9, and unmarked) need to have current limiting resistors at their base pins. Higher current switching transistors will require lower value resistors. So for Q6 I'd recommend about 390 ohm, T9 about 500 ohm, Q5 & unmarked about 5k. Later testing may reveal possible value changes depending on current flow requirements.

3) Q6 will now turn on "only" when both Q's are low, is this what is needed? Your recent comments about this do not match up so well.

Your comments:

a. "If either of the 556 circuits go low, I want it to cut the power to the circuit."
Defines a NAND function.
(0 1)=1, (1 0)=1, (0 0)=1, (1 1)=0

b. "If either are high, the output should be high. Then, it will turn off the PNP."
Defines an OR function.
(0 1)=1, (1 0)=1, (0 0)=0, (1 1)=1,

c. "If it is both are low, the circuit should be on."
Defines an OR function.
(0 0)=0

As written condition "a" contradicts "c" for input condition (0 0). To settle this you will need to redefine condition "a" or "c".

4) I don't yet see which supply voltage will be powering your logic gates. One way to define this on a schematic would be to include one or more by-pass capacitors connected from power to ground then list the IC's that they are associated with.

5)A good way to keep track of your logic signals is to add signal names next to the schematic lines. This way you can verify the logic just by following the signal names. For example the signal coming from S1 pin 2 could be named "S1", then later after passing through IC10 the signal name becomes "~S1" (or any way you choose to designate an inverted signal). This practice will help debug your logic during the design phase and help again during the debug phase.

6) Rather then showing unconnected lines for the motor locations it would helpful to draw in the connections for your motors. For example you can place simple I/O connectors to show where the + and - contacts will be.

7) IC2 pin 4 and IC8 pin 4, have their outputs shorted together. You need to provide another logic gate, a resistor, or some diode switching here depending on your expected logic.

Similarly IC4 pin 4 and unmarked transistor collector, are shorted together, as above you need to add logic, a resistor, or diode here too.

IC5 pin 4 and Q5 collector, same as above.

With logic gate outputs shorted together you cannot be sure if either will over power the other, still this is not a good idea (unless they have special output modes), in some cases this might burn out one or both parts. For the transistors, they will most likely over power the logic gates, but it might also burn them out.

If one output must dominate you may be able to place a resistor in the path of the other output.

If the two outputs need to be combined then use another gate to define the logic. If only simple logic switching is needed you may be able to use one or more diodes or resistors.

Overall you don't want one output to fight with the other output if they were to switch in opposite directions.

  • \$\begingroup\$ Okay, I am still working on some of the things you suggested, but I fixed 1 and 2. For 3, c should be if both are low, then it should be off. 4 I am trying to use 5v. 6 I am not sure how to do that in Eagle :(. I will work on the rest of them and have a new one by tomorrow. \$\endgroup\$ – electricviolin Feb 13 '15 at 23:47
  • \$\begingroup\$ Your revised condition "c" simplifies the logic, but I doubt this is what you want either as this would make the logic always = 1, the PNP would always be off. To resolve this I think all you need to do is create a condition statement defining when the logic = "0" and the PNP turns on. \$\endgroup\$ – Nedd Feb 14 '15 at 9:49
  • \$\begingroup\$ For item 6, I assume the Eagle version you're using has some type of component which is a 3 or 4 pin header. Looking at another Eagle schematic I see a component named "M04PTH", as a 4-pin header. If you can find this you can make a polarity free connection by wiring pins 1 & 4 to the motor-, and pins 2 & 3 to motor+. Later on if you determine you need a heavyer connector you can change to a terminal block style connector. PS - This question is still marked as open, if one of the answers has helped out the most it would be good if you clicked the check mark on the top left of that answer. \$\endgroup\$ – Nedd Feb 14 '15 at 9:56

Q5 and the unmarked transistor below it are connecting logic pin outputs to ground or + supply, that is not usually a good thing to do. If you want to over power a logic gate output with a transistor you should use a resistor directly after the gate output. That limits the current out of the gate. (You may need to explain the logic here to get a better answer.)

The H-bridges should work but the voltage across the motors might be lower than exoected, (this may or may not be a problem dependent on the motor type used). Check the spec on the transistor type being used for the value of Base current (Ib) that will fully saturate the transistors, (you may need to reduce the base resistor values). Running the transistors in saturation will give maximum voltage to the motors. It is also a good idea to add protection diodes on each transistor of the H-bridge to reduce any hi-voltage spikes coming from the motor. See this example:

For the inverters coming from the two transistors (Q5 and nearest other transistor) you have inverter pairs in parellel. One pair (IC6-IC7) is connected input-input to output-output, this can work if that is your intension. However the other similar inverter pair (IC8-IC5) are in parellel input-output to input-output plus another output gate pin (U2-4), this is not good at all. You should recheck you intended logic here.

The 556 sections look OK so far. To reduce the possibility of false triggering in a noisy circuit (like one with motors) it may be helpful to add small capacitors from each CV pin to ground, about 0.01uf should do.

You can also reduce your total chip count by using left over NOR or NAND gates as inverter gates, (just short the inputs together).


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