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I want to implement iris recognition algorithm on FPGA. before i want to start i want to make sure that fpga is the right choice for image processing.

I will use a camera ov7725 to connect to an FPGA. FPGA will receive the 30 frames/second and select the best image accorcing to image quality algorithm. FPGA then detect a iris circle on selected image and then do the jpeg2000 compression on it. the compressed image should be transferred to host machine via USB. once the alogorithm is done, i want to make a custome hardware and then commercialise the product.

i want to know if FPGA is the right choice for it? if not please suggest me a better option. l BR, Abdu

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    \$\begingroup\$ How much experience do you have with FPGAs? The tasks you're describing are highly complex. \$\endgroup\$ – duskwuff Feb 14 '15 at 7:05
  • \$\begingroup\$ only basic working knowledge.... \$\endgroup\$ – Abdul_lateef Feb 17 '15 at 3:36
  • \$\begingroup\$ An FPGA is almost certainly not the best choice parallelpoints.com/why-use-an-fpga \$\endgroup\$ – Martin Thompson Feb 24 '15 at 14:28
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Well, I am currently responsible for a project which performs hand tracking recognition using a SoC (FPGA + ARM Processor). We have not started to develop the solution in the PCB yet, but I think some considerations we have taken in the beginning may help you.

Yes, FPGAs are very interesting to perform this kind of recognition algorithms because it allows to parallelize many calculations. For example, in hand tracking you may generate several guesses where each articulation is and check all of them at the same time. It is a great advantage over CPUs

Of course, you would have to analyze your algorithm to know for sure if it would perform well in a parallel execution. And if it is the case, you may implement it using a FPGA.

Altera, for example, has been developing solutions to synthesize OpenCL language descriptions directly to FPGAs. This may help you, because a higher level language like that may speed up your work a lot.

I do have a small concern though. For my project, fully functional, reliable hand and finger tracking is very difficult to perform in real time. Even some people using GPUs to parallelize calculations have not achieved 30 frames per second. Are you sure a micro-controller would not do your job? In this case, using an FPGA and all the work to develop the hardware description would be an overkill.

There is another side of FPGAs that may increase your budget. You will probably have to buy a license for a simulator. I am not sure you are familiar with FPGA applications. You have your hardware description, you test it with a couple of test benches running on a simulator, and when you are sure you design works, you synthesize it and go to the FPGA.

If you don't have a simulator, your work will be painfully slow. Synthesis of a big design may take a couple of hours. FPGAs are complicated to debug. With Altera, for example, you have to reserve a memory on the FPGA to store signal samples to then receive the waveform. It is much harder than micro-controllers.

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  • \$\begingroup\$ Xilinx ISE includes isim, which is free. There are also open source simulators for verilog and VHDL. Icarus Verilog is one that I use regularly. \$\endgroup\$ – alex.forencich Feb 14 '15 at 8:20
  • \$\begingroup\$ @alex.forencich As far as I know, Altera offers a version of ModelSim for free which has a limitation of 10k lines of code. I am not sure if this amount of lines would be enough for the OP project, but I guess not. Of course he may use an open-source, but I am not sure how these simulators support Altera or Xilinx libraries. If you do, please, include in your answer. My school has licenses, my company has licenses, so I do not know a lot about open-source solutions. \$\endgroup\$ – gstorto Feb 14 '15 at 8:25
  • \$\begingroup\$ I'm not sure if the open source ones support the libraries, but generally the code I write does not use any of the libraries to aside from perhaps a high level wrapper that has clocking and specialized interfaces. I try to write vendor-independent code when possible, which means avoiding direct instantiation of primitives or higher-level IP unless absolutely necessary. I think isim also has a line limit or similar, but I think the simulation just slows down. \$\endgroup\$ – alex.forencich Feb 14 '15 at 8:40
  • \$\begingroup\$ let me make my requirement very clear. \$\endgroup\$ – Abdul_lateef Feb 14 '15 at 9:44
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    \$\begingroup\$ @Abdul_lateef: You should edit this additional information into your question, rather than leaving it as a comment on one of the answers. Few people will see it here. \$\endgroup\$ – Dave Tweed Feb 14 '15 at 12:21

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