I have an ADC sampling at 500MHz (It is collecting data from an Ultrasound sensor). I need to be able to stream this data to my PC (for the time being - this will be done through a wireless unit). I am looking for a computing solution that sits in between the wireless unit and the ADC. I am putting all of this on a robot and I am trying to keep it as small as possible (in terms of dimensions) and hopefully keep the power consumption low.

Is there a solution that is better than using an FPGA? I have read that it is very hard to get an FPGA to run at 500MHz and some kind of Parallel computing might be required? Does that mean I am supposed to use GPUs?

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    \$\begingroup\$ Are you serious, utra-sound at 500 MHz? \$\endgroup\$ Feb 14, 2015 at 14:31
  • \$\begingroup\$ Ok, so let us say that you are using a 10-bit ADC and wants to send this data at 500MHz. We arrive at the following rate: 5Gbps. If you are trying to transfer 5Gbps through a wireless link, I think it is a little bit utopic. \$\endgroup\$
    – gstorto
    Feb 14, 2015 at 14:35
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    \$\begingroup\$ What are you trying to achieve with such extreme frequencies? The wavelength of 250 MHz in air is about 1.3 microns, and air is extremely lossy at these frequencies. A 250 kHz sensor, sampled at 500 kHz or maybe 1 MHz, would make a lot more sense. \$\endgroup\$
    – Dave Tweed
    Feb 14, 2015 at 15:15
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    \$\begingroup\$ @DaveTweed who knows, maybe it's a skin-crawling robot. \$\endgroup\$
    – pjc50
    Feb 14, 2015 at 15:21
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    \$\begingroup\$ The sensor may transmit at 250 MHz but its bandwidth is almost surely only a fraction of that, probably less than 10%. You only need to sample at several times that bandwidth which would reduce the data rate considerably. \$\endgroup\$
    – Barry
    Feb 14, 2015 at 17:28

1 Answer 1


One solution is to use a demux to reduce the ADC sample rate, and take advantage of the large number of pins on the FPGA.

For example, the ADC could be clocked at 500 MHz, and the FPGA at a more reasonable 125 MHz. Then a 4:1 demux can be used - collecting 4 ADC samples for each tick of the FPGA. The bus becomes 4 times wider, so at each tick the FPGA needs to ingest 40 bits, not 10, but that's not difficult to deal with.

In my application, the 2Gsps ADC and 8:1 demux are sold as a pair, so its output becomes 88 bits at 250 Mbps. There's no other way to use the ADC.

I assume you won't be sampling for very long, at that rate. The processing requirements will be determined by how many samples need to be used, and how quickly you need answers. For example, you could use 10GbE fibre to transport the data from your robot to a regular PC, for offline processing, no exotic hardware or software required.

Regular off the shelf wireless links only work to maybe 100Mbps, and only in ideal conditions, not found on a moving robot. Something will need to buffer the whole signal before you download it. DRAM on the FPGA? Embedded PC? Good luck!

  • \$\begingroup\$ 125MHz is REALLY slow for a FPGA. With a Stratix IV, I could reach easily 250MHz. It depends on the kind of operations he is going to do with this data, and the resolution of the ADC. A 32-bit addition is perfectly possible at 250MHz, a 64-bit he would have to split it in two cycles. \$\endgroup\$
    – gstorto
    Feb 15, 2015 at 6:28
  • \$\begingroup\$ Yeah, you can go much faster than 125 MHz. I have a design on a Spartan 6 that works at 250 MHz. And the PCIe gen3 x8 core comes out at 256 bits at 250 MHz. The DSP slices on the Virtex 6 FPGAs can go up to 600 MHz and up to 700 MHz on the Virtex 7. \$\endgroup\$ Feb 15, 2015 at 7:31

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