I need help solving the circuit above. I don't understand how to analyse the op amp using the small signal model in order to calculate the Vout/V3, the input resistance (Rin) and output resistance (Rout).
Any help would be appreciated
The ideal opamp model can be used to calculate the gain.
Rin is ideally infinite, as the gate resistance of the MOS transistors are also infinite.
The gain can be calculated by finding the current thorugh the BJT at the output, and the output will be simply equal to this current times R5. THis current is also equal to [Vout(output of the inverter) - Vss ] / R3.
The output resistance is simply equal to R5||ric , where ric is the resistance seen from the collector of the bjt, you can have a look at the calculation of it in this document http://users.ece.gatech.edu/mleach/ece3050/notes/bjt/BJTBasics.pdf
What I don't understand is, why this circuit have different values for the supply voltages, i.e. VDD, VSS, or the ground symbol.. Therefore, I didn't calculate the currents, and I am not sure about the base voltage of the bjt.
The circuit can be presented as two cascaded amplifying stages - a CMOS amplifier and the next op-amp amplifier (incidentally, I do not see much sense in this cascading since there is no negative feedback in the CMOS stage). So the overall voltage gain will be a product of the two partial voltage gains.
Now about the gain of the op-amp part. First of all, we should understand what this circuit is. There is nothing interesting in the voltage source +Vss and the voltage divider R1-R2 - they serve as an offset (biasing) voltage source that shifts the virtual ground and the op-amp inverting input. This positive biasing is necessary since the input current should enter R3 (to flow from left to right through R3) so that the Q2 base-emitter junction to be forward biased.
The rest of the op-amp circuit can be considered as a "non-inverting inverting amplifier":) since, from one side, this is an inverting configuration keeping a constant virtual ground at the op-amp inverting input... but from the other side, still the output voltage VR5 has the same polarity as the input voltage Vin of the op-amp circuit (the CMOS output voltage). As the same current I = Vin/R3 flows throught the three resistors R3, R4 and R5, the overall voltage gain of the op-amp circuit is VR5/VR3 = R5/R3.
It is interesting to see the connection between this op-amp circuit and the common-emitter amplifier with an emitter degeneration - in both the amplifying stages with negative feedback, the gain is simply a ratio between two resistances (R5/R3 and -Rc/Re).