I am trying to figure out some sources of error in this circuit. Firstly, the lower FET (in the schematic) seems to dissipate more power and heat up faster than the top FET. enter image description here

The shcematic above shows my layout, though i cant simulate in LTspice due to numerous issues. One being the issue of getting my gate drive opto modeled, the other is a minimum timebase error.

If anyone has any clue as to what is causing the lower FET to heat up more than the upper one, i would be grateful to hear it.

Also, i am a little confused with the waveform across my halogen bulb(the load in the diagram, R = 0.5 Ohms when cool). The picture below shows what i am observing: enter image description here

This is with my PWM duty around 50-70%. The load waveform can been seen swinging around 32V peak. I expected to see a straight light form across the x-asis that is representing the time spent not conducting. However it seems to be an inverted sinusoid of a much lower magnitude. Any explanation of the waveform is certainly helpful to my inquisitive nature.

However, I would like to try figure out why my FETS are heating unevenly.

Any assistance is greatly appreciated. Thanks!

EDIT to explain operation: This circuit is not able to be simulated, i created the symbol for the gate drive opto so i could show the schematic. I will explain the operation: A 25V RMS AC source is used to power a Halogen Bulb. Two MOSFETS are connected with their sources and gates connected together - This allows the same gate drive as VGS for both is always the same.

C2 maintains a 35V DC level, with a diode (D1) to stop it discharging to to the supply when its potential drops below +35V.

The schottky, zener and 680Ohm resistor allow me to derrive 12V dc to Supply my gate drive optocoupler.The capacitor C3 is charged to the 12V zener voltage and supplies the gate drive optocoupler with the current it needs in a rapid fashion.

The gate drive opto coupler is powered by this 12V capacitor, Its input is a PWM signal and its output is a push pull configuration for fast gate switching. The 0.1Uf bypass capacitor (c1) is placed per the datasheet of the opto. Two resistors on the gate, a low value in series and a high value resistor to the source.

When the PWM duty is raised, current flows from +ve terminal of the supply and through the upper FET (M3) which is open, the body diode of the lower FET (M4)is biased so as to allow current to continue to flow back to the supply. The same happens when the supply polarity inverses, but this time M4 conducts fully open and M3 conducts via the body diode.

  • \$\begingroup\$ I am not following you with the first statement. You say that the gate voltage of the lower fet (M4) is at the level of C2? But C2 supplies around 34V dc for my 12V zener. so that the zener voltage can then charge a cap to power the gate driver at 12V. So the gates of both should be 12V when the PWM is high. Though i see what you mean with the loop i believe: When v1 is positive, the current flowing through the zener will take the route of the body diode back to the supply -Ve terminal. How can i avoid this? \$\endgroup\$ – engineeroverhere Feb 15 '15 at 19:25
  • \$\begingroup\$ In the schematic it appears you have a forward biased diode from bulk(source) to drain in M4. \$\endgroup\$ – HKOB Feb 15 '15 at 20:05
  • \$\begingroup\$ This is to allow control of AC using two mosfets. Without the body diode, the layout would not work \$\endgroup\$ – engineeroverhere Feb 15 '15 at 20:12
  • \$\begingroup\$ I have looked at this for too long. The circuit is not obvious. I suggest you switch the GD-opto with a big cmos inverter and simulate just to see if that can explain anything. \$\endgroup\$ – HKOB Feb 15 '15 at 21:02
  • \$\begingroup\$ i have edited the post to expand on the operation. Thanks for you time \$\endgroup\$ – engineeroverhere Feb 15 '15 at 21:17

When one MOSFET is heating up more than the other, it is usually one of two items:

  1. Higher resistance in one leg.

It appears that you have included a 0.5ohm resistor in one leg, therefore, most of the current will go the low resistance route - the other leg.

  1. In switching applications, the diode of one MOSFET is being used instead of simply turning it on during that portion of the cycle.

The diode has ~0.7V drop at the same current whereas if you simply turned on the MOSFET, this would drop to a much lower value, dissipating less power. This is why there are synchronous power supplies.


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