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When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage?

Update:

csum= csum + one_cnt[i* ('DPC_shift +1) +: ('DPC_shift +1)];

I have a query, is this synthesiable?

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  • \$\begingroup\$ @Plutonium smuggler ,Thanks Sir, but I can't find it. \$\endgroup\$
    – Carter
    Feb 16 '15 at 8:46
  • \$\begingroup\$ @Plutonium smuggler - can you provide the answer that you found in your link, please? What does it actually mean? Thanks. :-) \$\endgroup\$ Feb 16 '15 at 9:08
  • \$\begingroup\$ @Carter - Can you provide a bit more context please? The statement containing the expression and the lines before and after the statement, thanks. Are you sure it is not a typo? \$\endgroup\$ Feb 16 '15 at 9:09
  • \$\begingroup\$ @Greenonline I'm not exactly remember that. I can do tomorrow. \$\endgroup\$
    – Carter
    Feb 16 '15 at 9:30
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From https://stackoverflow.com/a/18068296/1544337:

Description and examples can be found in IEEE Std 1800-2012 § 11.5.1 "Vector bit-select and part-select addressing". First IEEE appearance is IEEE 1364-2001 (Verilog) § 4.2.1 "Vector bit-select and part-select addressing". Here is an direct example from the LRM:

logic [31: 0] a_vect;
logic [0 :31] b_vect;
logic [63: 0] dword;
integer sel;
a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]
dword[8*sel +: 8] // variable part-select with fixed width

If sel is 0 then dword[8*(0) +: 8] == dword[7:0]
If sel is 7 then dword[8*(7) +: 8] == dword[63:56]

The value to the left always the starting index. The number to the right is the width and must be a positive constant. the + and - indicates to select the bits of a higher or lower index value then the starting index.

Assuming address is in little endian ([msb:lsb]) format, then if(address[2*pointer+:2]) is the equivalent of if({address[2*pointer+1],address[2*pointer]})

It is often useful to search for full names of operators. I found this searching for 'verilog plus colon operator'.

Also see https://stackoverflow.com/a/17779414/1544337, which is linked to from the quoted question.

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  • \$\begingroup\$ Thanks sir, But it was used at vector. But I saw at this For statements. I'm not exactly remember but it does used like this. For~~()~~+:(~~). Total statement does not exact. but +: was used at for statement. \$\endgroup\$
    – Carter
    Feb 16 '15 at 9:29
  • \$\begingroup\$ @Carter please edit your question to include the code you're having trouble with. \$\endgroup\$
    – user17592
    Feb 16 '15 at 9:30
  • \$\begingroup\$ got it. I'll let you know ASAP. \$\endgroup\$
    – Carter
    Feb 16 '15 at 9:33
  • \$\begingroup\$ But Would you please let me know Are these all synthesisable? \$\endgroup\$
    – Carter
    Feb 16 '15 at 9:35
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    \$\begingroup\$ Indexed part select works fine in a for loop. I have used it this way several times before and xst has no issue with it so long as the right-hand side is constant. \$\endgroup\$ Feb 17 '15 at 6:00
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Update:

csum= csum + one_cnt[i* ('DPC_shift +1) +: ('DPC_shift +1)];

I have a query, is this synthesiable?

At least in the version of quartus I use if i is a signal then it won't synthisize. I found this out the hard way. It complains about the indexing not being constant despite the fact that the width is constant and the fact that it is quite happy to perform a single bit select with a variable index.

I find this very annoying as if the tool supported it then it would be a useful tool for extracting sub-words from larger words.

I haven't tried with other tools or with i as a loop counter.

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