What does "+:" mean in Verilog?

Question

When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage?

Update:

csum= csum + one_cnt[i* ('DPC_shift +1) +: ('DPC_shift +1)];

I have a query, is this synthesiable?

Answer 1

From https://stackoverflow.com/a/18068296/1544337:

Description and examples can be found in IEEE Std 1800-2012 § 11.5.1 "Vector bit-select and part-select addressing". First IEEE appearance is IEEE 1364-2001 (Verilog) § 4.2.1 "Vector bit-select and part-select addressing". Here is an direct example from the LRM:

logic [31: 0] a_vect;
logic [0 :31] b_vect;
logic [63: 0] dword;
integer sel;
a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]
dword[8*sel +: 8] // variable part-select with fixed width

If sel is 0 then dword[8*(0) +: 8] == dword[7:0]
If sel is 7 then dword[8*(7) +: 8] == dword[63:56]

The value to the left always the starting index. The number to the right is the width and must be a positive constant. the + and - indicates to select the bits of a higher or lower index value then the starting index.

Assuming address is in little endian ([msb:lsb]) format, then if(address[2*pointer+:2]) is the equivalent of if({address[2*pointer+1],address[2*pointer]})

It is often useful to search for full names of operators. I found this searching for 'verilog plus colon operator'.

Also see https://stackoverflow.com/a/17779414/1544337, which is linked to from the quoted question.

Answer 2

Update:

csum= csum + one_cnt[i* ('DPC_shift +1) +: ('DPC_shift +1)];

I have a query, is this synthesiable?

At least in the version of quartus I use if i is a signal then it won't synthisize. I found this out the hard way. It complains about the indexing not being constant despite the fact that the width is constant and the fact that it is quite happy to perform a single bit select with a variable index.

I find this very annoying as if the tool supported it then it would be a useful tool for extracting sub-words from larger words.

I haven't tried with other tools or with i as a loop counter.