It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that tests the DUT.
Anyway, there does seem to be a lot of terminology involved in this as well and at this point I only wish to know what is code coverage and especially functional coverage. These terms are also used with reference to SystemVerilog that I am trying to read about.
Just one more question here. What is a "configuration" in systemverilog? The book says "Generate configuration : Randomize the configuration of the DUT and the surrounding environment." What does that mean?