# Why do LDO regulators have so big a voltage drop?

Why do LDO linear regulators not use MOSFETs as the main component to be able to have minimal dropout=0 (well, depending on current, must be still a few mV)?

Or can one expect to build a 0-dropout regulator based on a MOSFET and an opamp?

• I've seen LDOs dropping only 50mV. Not good enough? – stevenvh Jun 17 '11 at 11:42
• Pretty good, but MOSFET should be able to do more :-) – BarsMonster Jun 17 '11 at 11:44

There are regulators with a drop out voltage close to 0 mV. Check figure 5 on page 6 in TPS73101, Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection.

Another example is LTC1844 - 150 mA, Micropower, Low Noise, VLDO Linear Regulator.

The problem with regulators at such low drop out voltages is that in those regions they have crappy parameters (line/load regulation and PSRR).

As to the part if it is possible to build such regulator with an op-amp and a discrete MOS device - yes, it is possible. You will have to use PMOS and take care of stability (it is not easy to make a feedback loop stable in such a configuration).

• I see, thanks... Exactly what I was thinking... P-MOSFET-based without any chargepumps:-D – BarsMonster Jun 17 '11 at 16:33
• If you have a 0V dropout you don't have no line regulation at all! :-) – stevenvh Jun 28 '11 at 10:15

If you want a super-low LDO, you need a device with an extremely-low input-to-output saturation voltage (i.e. a FET) and some way of having the control voltage higher than the input.

Using a BJT will always limit you to the $V_{CE}$ saturation voltage, plus you need sufficient base current to ensure the transistor will be on fully when necessary. Also, the $V_{BE}$ voltage has to be taken into account. If the base is 1V below the collector, then the emitter has to be more than 1V + $V_{BE}$ lower.

If you're using an N-channel FET as the series pass element, you need to get the gate high enough above the source for the FET to conduct fully. Many logic-level FETs need more than a volt. Many FETs with good $R_{DS(on)}$ need even higher than that. If you tie the gate to the input voltage, for example, you can expect that the $V_{GS}$ threshold voltage will be dropped across the MOSFET, making it a 'lossy' LDO as per your question definition.

A discrete LDO using a FET and a driver able to fully turn on the MOSFET (i.e. higher gate voltage than the input voltage) will allow you to make an LDO which will only have a series $R_{DS(on)}$ loss, theoretically. But then again, if you already have a higher rail available, why not use it as the regulator input and stop worrying about the super-low LDO?

• What about P-MOSFET & inverted control signal? – BarsMonster Jun 17 '11 at 13:03
• N-channel MOSFETs are electron majority-carrier devices, whereas P-channel MOSFETs are not. You cannot achieve the same low $R_{DS(on)}$ in a P-channel as an N-channel, even with the simpler control. Otherwise, it will still work. – Adam Lawrence Jun 17 '11 at 14:03
• @Madmanguruman - You can make PMOS to be have the same RDSon as nmos - it has to be just about 3x bigger then NMOS made in the same technology. The main problem with pmos based LDOs is that it is darn hard to make them stable and/or make them with decent parameters. – mazurnification Jun 17 '11 at 14:26
• Agreed - my statement was based on maintaining a constant package size for the part. – Adam Lawrence Jun 17 '11 at 14:44
• @mazurnification: Would there be any difficulty using an NFET but regulating the negative rail rather than the positive one? I know the more common circuit topology is to regulate the positve rail (7805's are much more popular than 7905's) but in a lot of applications it really doesn't matter. – supercat Jun 18 '11 at 1:21

Some LDOs use an external MOSFET:

http://www.micrel.com/page.do?page=/product-info/products/mic5156.shtml

I designed a discrete LDO linear regulator circuit using an n-channel MOSFET to make a negative voltage. This was 22 years ago, and I published it in an electronics magazine set up for charging SLA batteries at 13.8 volt.

Thousands were built in one form or another, and I did not have any stability problems. This old simple circuit could be configured with a p-channel FET and lower output voltages and these days the drop would be limited by the low MOSFET on resistance. SMD parts mean that discretes are not a penalty, so I know that really low drop is now possible.

• Got a reference for the article? – Peter Green Dec 26 '15 at 14:06
• Peter Green.In the pre-internet days I would Submit Articles to LEO SIMPSON who is an editor of the Australian Electronics magazine "Silicone Chip" The handwritten manuscripts that I submitted would sometimes be put in the circuits section.I am sure that it was published but did not win . – Autistic Dec 29 '15 at 9:26