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The schematic of the LM113 precision reference shows a 75pF capacitor integrated in the IC. Looks huge to me. What's the limit when integrating capacitor on-die?

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  • \$\begingroup\$ I never thought to associate '75pF' with 'huge', but then again, I come from a switching power background where thousands of microfarads are sometimes considered 'not enough'. ;) \$\endgroup\$ – Adam Lawrence Jun 17 '11 at 12:32
  • \$\begingroup\$ @Madmanguruman - I see what you mean. I can imagine very-high-power engineers thinking how you could possibly care about a single \$\mu\$A, too. :-) \$\endgroup\$ – stevenvh Jun 17 '11 at 12:37
  • \$\begingroup\$ Are you positive it's on the die, and not just in the package? \$\endgroup\$ – drxzcl Jun 17 '11 at 22:47
  • \$\begingroup\$ @Ranieri - it's most probably on the die. The other solution would be expensive, wiring-wise, especially since there seems to be another 30pF cap in the schematic. My guesstimate was that it would need only \$0.1mm^2\$. \$\endgroup\$ – stevenvh Jun 18 '11 at 6:00
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The limit is just what you're prepared to pay. In a 0.13 \$\mu\$ process it would be a shame to waste all this space on a cap; you could place probably 10 000 transistors there.
The LM113 is already old and has a far larger feature size, so it will take relatively much less space, compared to the complete die. Don't forget all the resistors. Those are also expensive in die real-estate terms.

Assuming a separation of 0.1 \$\mu\$ and a dielectric constant of 10 a 75 pF capacitor will be around 0.3 mm x 0.3 mm. Not that bad after all.

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For very large capaciatances it might make more sense for them to integrate in an op amp style capacitance multiplier, if it will get the job done. Complexity would go up, but the overall silicon size used might be far less than the equivalent full capacitor.

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