The background for this question is a Master level university group project, we're designing a class D sigma delta modulated amplifier which is part of a MIDI synthesizer on a large FPGA.
We're currently attempting to reach 12 bits of performance at 20hz - 20khz final output frequency at over 80% percent power efficiency. Currently we are deciding between trading off output frequency and required noise shaping loop order (2 or 3rd degree).
Now, the issue at hand is inexperience estimating how fast we can drive our external output switches (directly or with drivers). A second order loop would theoretically call for oversampling of 40x ish, to reach 12 bit performance. Which means driving the switches at a frequency of 1.6 Mhz.
Third order loop would bring this down to 960 khz or so at the expense of extra complexity and loop stability considerations.
Exploring high performance mosfets in the ~500mA capability area and low gate charge they seem to have rise and fall times around 5-10ns and turn-off/on delay times of order 10-20ns. Assuming a 1.6Mhz output frequency it means transition times are seemingly creeping up to 5-15% of the period.
What switching frequencies can we expect to reasonably achieve for 50-100mW power delivery either entirely discretely or with the help of mosfet drivers. If necessary we can fabricate a pcb with smd parts and proper layout ?