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The background for this question is a Master level university group project, we're designing a class D sigma delta modulated amplifier which is part of a MIDI synthesizer on a large FPGA.

We're currently attempting to reach 12 bits of performance at 20hz - 20khz final output frequency at over 80% percent power efficiency. Currently we are deciding between trading off output frequency and required noise shaping loop order (2 or 3rd degree).

Now, the issue at hand is inexperience estimating how fast we can drive our external output switches (directly or with drivers). A second order loop would theoretically call for oversampling of 40x ish, to reach 12 bit performance. Which means driving the switches at a frequency of 1.6 Mhz.

Third order loop would bring this down to 960 khz or so at the expense of extra complexity and loop stability considerations.

Exploring high performance mosfets in the ~500mA capability area and low gate charge they seem to have rise and fall times around 5-10ns and turn-off/on delay times of order 10-20ns. Assuming a 1.6Mhz output frequency it means transition times are seemingly creeping up to 5-15% of the period.

What switching frequencies can we expect to reasonably achieve for 50-100mW power delivery either entirely discretely or with the help of mosfet drivers. If necessary we can fabricate a pcb with smd parts and proper layout ?

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  • \$\begingroup\$ You will need MOSFET drivers and careful layout, but switching FETs at 1-2 MHz is no problem. Take a look at TI's LM5113 FET driver. It's meant for GAN FETs but it will work with low threshold silicon FETs as well. It has some data on switching up to 5MHz. There are plenty of other FET drivers out there as well. \$\endgroup\$ – John D Feb 18 '15 at 16:07
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Assuming 200mW peak power delivered into 8 ohm load, that gives peak voltage and current of 1.26V and 15mA. V peak to peak required is 2.52V. This is within the realm of logic output with no FET at all, perhaps even directly off of the FPGA, or a simple buffer. Have I forgotten to consider something?

If FETs are used, given the low power level, it does not appear any "special" drivers are needed as long as the drive signals have the correct voltage levels. The switching frequency would be limited by concerns which some you have mentioned and few MHz should be simple. Also, at the low power level, some datasheet values are likely to be quite conservative because they are specified at relatively high voltage and current.

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  • \$\begingroup\$ The problem with direct drive from a logic circuit is that those switches won't go low enough impedance when on to attain the efficiency they want into a 8 Ohm load. Hmm, ganging a bunch of line-driver digital outputs together might get you there though. That would certainly make the control very easy. Even if you dedicate a whole chip to each of the four drivers, that's no worse than 4 separate FETs, and a lot simpler to control. \$\endgroup\$ – Olin Lathrop Feb 18 '15 at 19:32
  • \$\begingroup\$ The switch does not see just the impedance of the load, it sees the combined impedance of the load and the inductor. The current is easier to work with. With the stated assumptions, the peak current through the inductor to the load would be around 15mA. \$\endgroup\$ – rioraxe Feb 19 '15 at 16:09

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