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All CMOS digital integrated circuits I've ever seen connect all the nFET substrates together to GND.

In particular, the IC CMOS NAND gate has one nFET that has its substrate connected to GND, but its source pin connected to some other internal node.

If I build a NAND gate out of discrete nFET and pFET transistors for educational reasons, do I need to duplicate that substrate connection by using a 4-terminal transistor (with the substrate separately pinned out) to get it to work? Or would that NAND still work just as well with 3-pin discrete transistors, with the substrate "incorrectly" connected to the source pin?

Is there something magic about a 4-terminal transistor that has a "source" pin not tied to its substrate, such as the ones inside an IC, that can't be duplicated by an individual discrete 3-terminal transistor?

(This question was inspired by some coments at Recomendation for a digital inverter made of discrete components ).

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The short answer is that you don't need 4 terminal FETs to build CMOS logic.

Some Background:

In a simple CMOS process, (P-type Wafer, N-Wells) the substrate contact is directly connected to the conductive wafer. This means that the body terminal of all NFETs are basically shorted together. A similar effect happens with the PFETs, although it isn't as absolute. They aren't shorted together to improve performance, but because it is cheaper and easier to manufacture.

This brings up a question: If we had to tie the body terminal of all NFET devices together, what voltage would we like it to be? For NFETs, the body-source and body-drain connections normally look like reverse-biased diodes. In order to maintain these diodes reverse-biased, the body voltage must be less than \$V_D \mbox{ or } V_S + 0.6\mbox{ Volts}\$. Typically this is done by tying the substrate/body to the most negative voltage present in the system. In digital systems, this is usually ground \$V_{SS}\$. The body terminal of PFETs is typically tied to the most positive voltage, or \$V_{DD}\$ for similar reasons.

For 3-terminal FETs, where the source and body have been internally shorted, the internal diodes will never be forward-biased if the source is always at a lower voltage than the drain. If you are stuck with 4-terminal transistors building discrete gates, it will work with the bodies connected to \$V_{SS}\$ and \$V_{DD}\$, and it will also work with the body shorted to the source.

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  • \$\begingroup\$ Four-terminal FETs aren't needed for "conventional" CMOS logic circuits which are expressed as combinations of "nand" and "nor" gates, but there are some tricky circuits where transistors can work both ways. For example, consider a five-input circuit to compute AB+CD+AED+BEC. Ten transistors (five N-channel, five P-channel), but the transistors for input E have to be capable of switching current in both directions. \$\endgroup\$ – supercat Aug 29 '11 at 23:42
  • \$\begingroup\$ @supercat - Sure, if you start to do fancy things such as transmission gates / pass transistors, then a common substrate is necessary. This allows you to "switch" the source and drain. However, I would think that topology would be much more likely to be found inside a chip than on someone's breadboard. \$\endgroup\$ – W5VO Aug 30 '11 at 5:43
  • \$\begingroup\$ The fact that four-terminal FETs are not as widely available as 3-terminal ones does discourage the use of such tricks in discrete-transistor logic. On the other hand, a desire to save parts can inspire tricks which might be less common on a chip. Back around 1980 (I was about 10), I designed an XOR gate with two transistors, two diodes, and a few resistors (current at +12 was 'true'; no current was 'false'). If the transistors had been FETs rather than BJT's the diodes wouldn't have been needed. I've never heard of an NMOS chip using such an XOR gate implementation internally... \$\endgroup\$ – supercat Aug 30 '11 at 14:21
  • \$\begingroup\$ ...although it would have been an even slicker design than the BJT version (with NMOS FETs, it would be XNOR rather than XOR). Simply wire the source of each MOSFET to one input, and the gate to the other input. Tie the drains together with a pull-up. If one input is high and the other low, the output is low; otherwise it's high. The output drive strength would be weaker than the input drive strength, but even adding inverters to both inputs would yield a 4-transitor 3-resistor XNOR gate--smaller than the other NMOS versions I've seen. \$\endgroup\$ – supercat Aug 30 '11 at 14:28
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In addition to what W5VO has said, the 4-terminal transistors are also useful for analogue electronics on CMOS processes.

In such cases, sometimes, the body of the transistor may be connected to some intermediate voltage instead of VDD or VSS. This can be used to modulate the VTH of the transistor using the body effect. This is described here.

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You can make logic without separating the substrate / bulk / body connection from the source. But if you wanted to experiment and make circuits that are just like CMOS ICs so you need 4-terminal MOSFETs, you can use CD4007UB.

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