I've gone through two of my text books and consulted my teacher but nothing seems to clarify my doubts.

The two versions of race which I've been taught are -

  1. When the S and R inputs of an SR flipflop is at logical 1, then the output becomes unstable and it is known as race condition.

  2. When the S and R inputs of an SR flipflop is at logical 1 and then the input is changed to any other condition, then the output becomes unpredictable and this is called the race condition.

Which one is right? Or, are both of them wrong, if so, what is actually race?

  • 2
    \$\begingroup\$ Is this question about latches or about flip-flops? Some of the answers are describing latches but calling them flip-flops. The distinction is discussed here: electronics.stackexchange.com/questions/21887/… \$\endgroup\$ – nobar Feb 19 '15 at 15:47
  • \$\begingroup\$ i'm talking about flip-flops (edge triggered mechanism) \$\endgroup\$ – Soham Feb 19 '15 at 15:48
  • \$\begingroup\$ The question is worded in terms of S and R, so it is obviously not about clocked logic. If Lucyfer meant to ask something different he could edit the question, I think it is not propper to have a comment not just carify a question but turn it around 180 degrees. \$\endgroup\$ – Wouter van Ooijen Feb 19 '15 at 17:45
  • \$\begingroup\$ @WoutervanOoijen I agree it would be a good idea for the OP to clarify in his question that he wants edge-triggered clocked SR flip-flops. Actually all of the the current answers (including mine, which I deleted) used latches. I will concede the OP did say flip-flop in his original post, not latch, and I didn't pick up on the difference. This is an edge-triggered flip-flop -- note that it requires two SR latches in series. \$\endgroup\$ – tcrosley Feb 19 '15 at 17:47
  • \$\begingroup\$ In my book an edge triggered thingy has a single data input, and a thingy with S and R inputs is a simple cross-coupled NAND or NOR. That is more constant than the FlipFlop/Register/Latch terms, so I can only interpret his question as referring to the simple circuit. But I extended my answer to cover level and edge triggered thingies. \$\endgroup\$ – Wouter van Ooijen Feb 19 '15 at 18:34

A race condition is a timing-related pheonomenon. A standard S-R FF (two cross-coupled NAND or NOR gates) is stable for any stable input.

enter image description here

The 'fun' is in the S=1 R=1 input, the memory situation. The state of the FF depends on which state came before the 11, if it was 01 the FF is in Q=1 state, if it was 10 the FF is in the Q=0 state. This is the classical memory effect of a FF.

But if it was 00 and both inputs changed to 1 suffiently close to each other in time, the FF can enter a metastable state, which can last significantly longer than the delay time of the gates. In this state the outputs can either slowly drift towards their final sate, or show a damped oscillation before settling on the final state. The time required to settle is unbounded, but has a distribution that quickly falls off for t >> gate-delay.

In normal operation, from 00 input, one input becomes 1, and the feedback loop in the flipflop propagates this (or rather, the remaining 0 input) through both gates, until the FF is in a stable state. When the other input also turns 1 while the propagation from the first is still taking place, that also starts to propagate, and it is anyone's guess which one will win. In some cases neither wins immediatyely, and the FF enters the metastable state.

The race condition is that, from a 00 input state, one input changes to 0, and the second one also changes to 0 before the effect of the first change has setteled. Now the effects of the two changes are 'racing' for priority.

The explanation stated is for a simple Set-Reset FF (or latch, or how you want to call it). A level-triggered circuit (I would call that a Latch) can be thought of as a RS-FF with both inputs gated by the enable input (CLK in this diagram):

enter image description here

In this circuit, a simulatenous 00 -> 11 transition of the hidden 'inputs' of the cross-coupled NANDS still causes a race condition. Such a transition can occur (due to the delay caused by the inverter) when the D input changes simultaenously with the CLK input changing from 1 to 0.

A real clocked (edge-triggered) memory circuit can be thought of consisting of two latches, enabled by the opposite clock levels (master-slave arrangement). Obviously the first latch is still susceptible to the same race condition.

enter image description here

PS googling for the appropriate pictures I got them from How 1-bit was stored in Flip flop? :)

  • \$\begingroup\$ forgive my stupidity ,but i still can't wrap my head around what "race-around" actually means from this answer. \$\endgroup\$ – Soham Feb 19 '15 at 9:45
  • \$\begingroup\$ added some text \$\endgroup\$ – Wouter van Ooijen Feb 19 '15 at 11:03
  • \$\begingroup\$ This answer is for a latch, not a flip-flop. The OP was interested in clocked SR flip-flops. See comment under his post. \$\endgroup\$ – tcrosley Feb 19 '15 at 16:44
  • \$\begingroup\$ The picture you added is not an edge-triggered SR flip-flop (which is the topic of this question), it's an edge-triggered D flip-flop. See the image I linked to in the comment under the question, that's an edge-triggered SR flip-flop. I don't know why you are bringing in D flip-flops at this point. Your comment above the bottom picture about the first latch being susceptible to the same race condition obviously doesn't apply to D flip-flops, the two inputs to the latch can never both be 1. \$\endgroup\$ – tcrosley Feb 19 '15 at 18:02
  • \$\begingroup\$ They can, for a brief moment, due to delays. And a brief moment is all that it takes to get a (possible) metastable situation. \$\endgroup\$ – Wouter van Ooijen Feb 19 '15 at 18:36

Race around condition in digital circuits occur when the final state of the output depends on how the inputs arrive.

Digital circuits have inherent delays. So it is possible that one of the inputs arrive a little earlier or later than others ie the inputs which were meant to be present at the same time actually arrive at different times due to different delays along their path.

As a result of this, the output changes unpredictably. In other words, there is a race among the inputs as to which one will affect the output. Generally this takes the form of spikes, which can be both high or low.

For your case :

enter image description here

Consider what will happen if both S and R are high.

Assume q = 0 and q' = 1 initially. Then

If A arrives before B , Q will change to High which will momentarily set Q' low which in turn should have ideally kept Q high and so on.

Now after a moment, B arrives ( very short duration). This will turn Q' High which in turn will set Q High.

You can check to see what happens when B arrives before A.

Now actually, there are 2 things happenning here :

1) The output depends momentarily on which input arrives first. This in essence is the race condition.

2) The final state is q = 1 and q' = 1 . This is NOT race condition. This is merely an invalid state. Ideally, Q and Q' must be opposite, which is not the case here.

I hope I am correct.


All the answers enter image description here

Firstly its not race around condion....don't confuse it....its Race Condition.....

When S=R=1 Q=Q'=1. Its well defined..but the problem arises when both S and R changes simultaneously to 0 from 1(high to low)

The transistors will try to come out of saturation...

Now both transistors Qr and Q's will try to come out of saturation...but as the saturation delay if the transistors can rarely be equal in mass production...the transistor with less saturation delay will win..and will latch the circuit...

If Qr is faster then voltage at M will fall and Q=0 If Qs is faster then voltage at N will fall and Q'=0

Thus output is unpredictable

Even if speeds are equal then also outputs Q and Q' will oscillate between 1 to 0 and then 0 to 1 Thus output is unstable...


I think case 1 is appropriate. ie., When both the inputs of a SR latch is '1', then the output is unstable.

Now from S=R='1' the input is changed to S=R='0' at this condition is output is supposed to be the previous state. But previous state was unstable. So the output may lock to either '1' or '0'. You can not predict.

So case 2 is correct if the input was changed from '11' to '00'.

  • \$\begingroup\$ well if you use nor gates then it is 11 \$\endgroup\$ – Soham Feb 19 '15 at 15:49

Whenever we provide 1 to both J and K in the JK Flip Flop, the output is supposed to complement the previous output. This is called race around condition(similar to the same concept in "operating system", where the final output depends on the sequence by which processes are executed).

To overcome this problem, we use master-slave flip flop.


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