Yes, your P MUX is very correct:
0+0 inhibits carry (switch carry for 0)
0+1 propagates carry (switch carry through)
1+0 propagates carry (switch carry through)
1+1 generates carry (switch carry for 1)
Especially advantageous now to use a switched MUX, never a combinatorial.
Why? All multiplexers can switch simultaneously with regard only to A vs B.
Carry then ripples with almost no propagation delay through closed switches.
Using combinatorial logic slows this down to a ripple carry and no faster...
Now you might want a chain of borrow MUX to handle subtractions:
0-0 propagates borrow (switch borrow through)
0-1 generates borrow (switch borrow for 1)
1-0 inhibits borrow (switch borrow for 0)
1-1 propagates borrow (switch borrow through)
Note this MUX plan works with a non-inverting borrow.
SUM and differences are same XOR3(A,B,C) for A+(B+C), A-(B+C), B-(A+C)
I would rather an 8 way MUX for SUM than feed a 4way with the inverter.
Feed it an 8bit carry conditional truth table that can do any function.
Not just ADD. Even if stuck by some rule of 4way only, I would feed it
a truth table.
And then you might want to propagate carry through all slices unchanged.
Then you can set your truth table to give A vs B, AND vs OR, etc..
Beware if you go with 74CBT3253! There are two flavors of this dual MUX.
Some offer independent /OE0 /OE1 shutdowns, others offer all or nothing.
For example, you might want to shutdown the borrow MUX when using carry.
That can be real difficult if you order the wrong chip thinking all same.
Pay careful attention any suffix letters and doublecheck your spec sheet.
This MUX topology closely resembles a carry skip adder. Except it doesn't
ever skip anything. Fast by virtue of switching, not skipping. Therefore
I call it a carry switched adder, unless it already has some other name?
Konrad Zuse invented this trick for the first relay computers, and might
already have named it.