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How can i implement the full adder of two 1-bit numbers using only multiplexers 4/1? I created a truth table for a one-bit full adder, which looks like this:

enter image description here

A = first bit
B = second bit
Pu = bit from lower position (used to create an adder for multiple bit numbers)
S = sum
P = transfer to higher position (e.g. if A=1, B=1 and Pu=0, the sum is 0 and transfer 1)

I made K-maps and used AB as selection inputs of a multiplexer and Pu as information input.

And finally got to this solution:

enter image description here

Is it correct?

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    \$\begingroup\$ Yes. It is correct. \$\endgroup\$ – nidhin Feb 19 '15 at 13:17
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Yes, it's correct.

This is the sort of optimization that used to happen manually in the old days of FPGAs and before that with PALs. You had to rejigger your result based on selection and minimal logic gates.

I've not run across this solution, but then I've never been stuck with just multiplexors.

Oh incidentally,... one more multiplexor would do that inversion (generating the invert in the previous stage), so you could easily create a large adder with a three-pole switch for each binary digit. No logic needed. Nice.

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