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How can I implement the comparator of two 2-bit numbers using decoders DEC 2/4 and required logic gates? That comparator will be used to compare two 4-bit numbers. The comparator only has one output to show if the first number is bigger than the second. I created the truth table for the comparator:

enter image description here

A1 - higher positioned bit of the first number
A0 - lower positioned bit of the first number (mistake in the table)
B1 - higher positioned bit of the second number
B0 - lower positioned bit of the second number
X - is 1 if A>B <=> (A1>B1) + (A1=B1)(A0>B0)

And here's my solution using decoders 2/4 and required logic gates:

enter image description here

Even though I did the task, I'm not completely sure if it's correct.
What I don't understand is: How do these decoders function? It's like X will always be 1 if the conditions are made, the output of the comparator will never be 0. Please correct me if I'm mistaken or correct the solution.

Edit, new solution using the true logic of decoders (not demultiplexers), please check if it is good:

enter image description here

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  • \$\begingroup\$ What is the bottom input for the decoders you are using? Looks like they are DeMuxes, not decoders. \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 17:05
  • \$\begingroup\$ It's the CS (chip select) signal. \$\endgroup\$ – A6SE Feb 19 '15 at 17:07
  • \$\begingroup\$ And what is the output of a non-selected chip? Tri-state? So what will be the output of a gate which has a tri-state inputs? In your drawing, for A="00" none of the rightmost decoders will be selected, so what will be the output? \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 17:08
  • \$\begingroup\$ The output of a non-selected should be 0, right? And if any of the gates outputs 1, then A>B and X=1. \$\endgroup\$ – A6SE Feb 19 '15 at 17:10
  • \$\begingroup\$ Yep, that's what bothers me, should I just put zero next to it, or somehow connect it to X? \$\endgroup\$ – A6SE Feb 19 '15 at 17:11
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First let's see how to implement a function using single decoder. It is a straight-forward task having the truth table. Decoder will output 1 on the lines selected by the input, so if we just "or" the outputs corresponding to the truth table lines with X=1, we will get the exact required function: enter image description here

Unfortunately there is no straightforward way to convert it to 2->4 decoders. But maybe we can divide the original function to smaller ones, suitable for 2->4 representation? Let's look at it. After some manipulations I've omitted here, the function can be represented as $$A_1B_1'+A_0B_0'(B_1'+A_1)$$ So we can see here three different 2-variable functions combined with ANDs and ORs:
1) \$A_1B_1'\$
2) \$A_0B_0'\$
3) \$B_1'+A_1\$
while (1) and (3) are functions of the same variables and can share decoder.

So the solution would be: Implement functions (1)-(3) using the method above, and interconnect the outputs using the gates: enter image description here

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  • \$\begingroup\$ What is the second output of the B1A1 decoder? B1=1 and A1=0? \$\endgroup\$ – A6SE Feb 19 '15 at 19:11
  • \$\begingroup\$ Look at the little numbers near the splitters. '1' stands for the MSB. The second input is for A1B1 = "01", as you said. \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 19:12
  • \$\begingroup\$ OH OK, if we had multiple inputs, only MSB would be 1 and the rest 0? \$\endgroup\$ – A6SE Feb 19 '15 at 19:14
  • \$\begingroup\$ No, I guess you are looking at the wrong numbers. Look at the top schematic, it has a splitter with bits numbered 3-0 where 3 is MSB \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 19:15
  • \$\begingroup\$ OH, ok, hahah, sorry for the inconvenience, i'm at the beginning of my studies. Big thanks for everything! \$\endgroup\$ – A6SE Feb 19 '15 at 19:17
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Inputs of first decoder be A0 and A1. Outputs \$N_0, N_1, N_2\$ and \$N_3\$ (\$N_0\$ will be high for A='00')
Inputs of second decoder be B0 and B1. Outputs \$M_0, M_1, M_2\$ and \$M_3\$

Let the final output be Y. Then,

If A = '00' then, \$Y = `0`\$
if A = '01' then, \$Y = M_0 \$
if A = '10' then, \$Y = M_0 + M_1\$
If A = '11' then, \$Y = \overline{M}_3\$

Or,

$$Y = N_1M_0 + N_2(M_0+M_1) + N_3\overline{M}_3$$

Hardware requirement is 2 decoders + 6 gates

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  • \$\begingroup\$ My logic is, no inverters XD Why didn't I come up with them? I don't know, thank you very much! \$\endgroup\$ – A6SE Feb 19 '15 at 18:37

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