I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator.
Problem is, there are tons of information out there and almost all good programs need an expensive license.
I'm going to be given a Xilinx FPGA (probably a Virtex-6) and so I will have a valid license to use Vivado HLS and ISE. So now, my idea on how to convert a C algorithm to the FPGA is this:
1 - Convert the algorithm from C to VHDL and optimize with Vivado HLS (already understood from tutorials how to do this step)
2 - Use the newly generated VHDL files in ISE to generate a bitstream (no idea how to do this)
3 - Use the Xillybus to connect a C program with the FPGA (with the bitstream) and send/receive information to be able to see the outputs.
Am I on the right way and am I lacking some step? About step 2, it is straigh-forward to generate the bitstream in ISE or to I need a lot of knowledge about port-forwarding?