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I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator.

Problem is, there are tons of information out there and almost all good programs need an expensive license.

I'm going to be given a Xilinx FPGA (probably a Virtex-6) and so I will have a valid license to use Vivado HLS and ISE. So now, my idea on how to convert a C algorithm to the FPGA is this:

1 - Convert the algorithm from C to VHDL and optimize with Vivado HLS (already understood from tutorials how to do this step)

2 - Use the newly generated VHDL files in ISE to generate a bitstream (no idea how to do this)

3 - Use the Xillybus to connect a C program with the FPGA (with the bitstream) and send/receive information to be able to see the outputs.

Am I on the right way and am I lacking some step? About step 2, it is straigh-forward to generate the bitstream in ISE or to I need a lot of knowledge about port-forwarding?

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  • \$\begingroup\$ If your VHDL is designed for synthesis, step 2 basically is just pushing one button in Vivado (then reviewing bugs, correcting your mistakes, and doing it again until you've fixed all bugs). \$\endgroup\$ – The Photon Feb 19 '15 at 17:40
  • \$\begingroup\$ That 1 button push is in ISE/Vivado and not in Vivado HLS right?And that button you're referring to generates the final bitstream? \$\endgroup\$ – João Pereira Feb 19 '15 at 17:42
  • \$\begingroup\$ Is it really complex algorithm? Maybe it worth just to reimplement it for hardware in the right way.. \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 17:50
  • \$\begingroup\$ Definitely in ISE. I haven't used Vivado much yet. If you push the button to generate a bitstream it will do all the earlier steps (synthesis, mapping, place & route) in the workflow for you if they haven't been done. \$\endgroup\$ – The Photon Feb 19 '15 at 17:55
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    \$\begingroup\$ Vivado can not be used for devices prior to the 7-series. In common:C to HDL translation does not save as much time as the flyers predict. More over users also need to know the underlying hardware to choose the right synthesis hints. \$\endgroup\$ – Paebbels Feb 19 '15 at 20:18
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Answering your comment question here where I have more space. Let's say you have an application you've designed on a linux box, and it runs an algorithm you wrote for counting the number of cat pictures on the internet. Now it runs but it's slow because there is a lot of cat pictures to go through, so you want to accelerate it in hardware.

So you use this tool to write OpenCL code which is in C but with some restrictions on form because it's going to be "compiled" to run on an FPGA. The call this portion of the code kernels. Now these kernels are going to be synthesized and run on the FPGA, maybe you have 1 or maybe you have a 100 working parallel.

You're doing all this right in your application, inline, so when you get to the point of actually counting the cats you're using their APIs to do the processing on the FPGA.

I just saw your other comment that it's not out yet, I know Altera's stuff has been out for a while you can find a bunch of design examples here

All that said it depends what your goal here is, do you want to learn how to write verilog, test benches, and be an FPGA designer? Or are you looking to just accelerate algorithms or functions using hardware without doing all that?

Like any tool-set, which one to use depends on the job at hand.

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  • \$\begingroup\$ Ty for the good and complete answer and for that Altera's link. Unfortunately the FPGA I'm going to use is from Xilinx so I guess I won't be able to use Altera's SDK right? About your question, in the 1st phase the goal is just to accelerate algorithms and see them implemented in FPGAs, so Altera's SDK and Xilinx' SDAccel would be enough. If I'm right about not being able to use Altera's SDK for a Xilinx FPGA and knowing that SDAccel is not yet out there, my solution is then Vivado HLS(program that I now understand well because of the long days reading tutorials) and then Vivado to ... \$\endgroup\$ – João Pereira Feb 20 '15 at 16:12
  • \$\begingroup\$ ...communicate with the FPGA. Do you agree? \$\endgroup\$ – João Pereira Feb 20 '15 at 16:13
  • \$\begingroup\$ Yes sounds like it, it will be a good learning experience anyway. \$\endgroup\$ – Some Hardware Guy Feb 20 '15 at 16:21

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