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I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and run it in an FPGA. Everything is going well so far, I started implementing the design in Verilog HDL a few days ago and got a very simple version working. Now the problem: I got in touch with some people that have been involved in hardware design for years and they suggested that before I go any further I should shift to using SystemC for the implementation. Now, made me very very confused because this was my thought:

Verilog -> As an HDL language specifically targets hardware design. Has some levels of abstraction like structural and behavioural Verilog, but it is a very neat form of specifying the RTL of a design. You can definitely synthesise it using a bunch of tools depending on the FPGA you choose (in my case I am using Xilinx Vivado 2014 and Zynq boards). On the down side plain Verilog does not offer enough abstraction for verification and that is why you have stuff like System Verilog.

SystemC -> This is a C++ class library that effectively introduces the concept of time in C++ and allows you to do an event driven simulation. Clearly it is a lot more high-level than any HDL and things here can be implemented much quicker. This makes it a very good tool for stuff like verification and even implementation of simulators so that people can start designing drivers and things for a chip before the thing is actually manufactured. Apparently, there is also a subset of SystemC that is synthesisable (I think even Xilinx Vivado can do this) and in some cases it enables SystemC to be used to design very large systems where a higher level of abstraction is handy.

So, my questions are:

  1. Are these notions of what systemC and Verilog (or HDL languages if you like) correct?
  2. When should I use SystemC and when Verilog?
  3. I am told that even in Verilog, using a lot of behavioral code can be a bit problematic in critical sections of the implementation because you are basically giving a lot less constrains to the synthesis tool on how to synthesise it. With a higher level of abstraction wouldnt this be a problem? i.e. If i use systemC I might end up with a very slow, power hungry, large design...
  4. The person that suggested SystemC mentioned that it looks like I am doing "architectural exploration" and that is why he would prefer Verilog. What exactly does that mean? I was under the impression that the architecture typically refers to the instruction set and the microarchitecture to an implementation of an instruction set (so the microarchitecture is the actual rtl that executes the instructions). So does architectural exploration mean that he thinks I am implementing a processor to see how feasible an instruction set is?
  5. He said that an argument for using SystemC is that its a lot easier because it is higher level of abstraction than an HDL. He also claimed that it was easier to get the timing of the design right. To what extent is this true?

Help would be greatly appreciated, I am a bit confused and finding it difficult to get clear information about this online. Thanks!

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  • \$\begingroup\$ Hi, can I ask which academic course it was? \$\endgroup\$ – Reflection Oct 5 '15 at 0:19
  • \$\begingroup\$ Hi, I studied Computer Science. Strictly speaking this is not part of the standard course, I chose to build a processor based on the Transputer for my master thesis from the ground up. \$\endgroup\$ – Andrés AG Nov 3 '15 at 21:54
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Your friend either misunderstood what you are doing or was thinking of SystemC as a preliminary step. An HDL is the only choice In any case, and I would suggest you use synthesizable SystemVerilog that is powerful enough to do a lot of exploration whole being essentially the same as Verilog for everything else.

  1. Partially. You distinguished between Verilog as an HDL, SystemVerilog as a verification language, and said that SystemC has higher abstraction but also a synthesizable subset. There are two errors here. First, SystemVerilog is also an HDL with a fully synthesizable subset that could be resumed as a Verilog with obvious fixes (e.g. one single logic type for wires) and many synthesizable abstraction mechanisms (e.g. Interfaces). It is supported by many tools including Vivado. SystemC on the other hand, is not directly synthesizable (not even any subset), it is meant for higher level modeling and architectural exploration though some subset of it can be fed in a High Level Synthesis tool such as Vivado HLS that then translates it into synthesizable (though human-unreadable) Verilog.

  2. Verilog and the synthesizable subset of SystemVerilog are languages for HW design, usually used to describe HW at a register-transfer level, i.e. as a set of blocks like registers, combinational functions, finite-state machines etc. Verilog-2001 can also appropriately describe hw as a gate-level netlist, while SV can also be used to a much higher level of abstraction hence its verification capabilities. On the other hand, SystemC is appropriate for high level modeling of systems in which entire blocks are described only in a high level behavioral fashion. It is also very powerful for architectural exploration, i.e. varying parameters and characteristics of an architecture and evaluate changes in the overall performance.

  3. That is true only if you try to describe things in a non-RTL fashion while developing an RTL model. For example, the right way to describe a block performing a repetitive multiply-accumulate is a finite state machine driving a combinational multiplier, a combinational adder, and a register - if by behavioral you meant describing this as in software (a for loop) then yes, behavioral code won't work. If you meant describing each of the blocks I described (mult, add, reg and FSM) via always blocks, that is perfectly fine and will work out in a netlist realizing exactly what you specified with excellent results (often better than a exceedingly structural approach that limits the capability of the synthesis tool to optimize logic). In fact, SystemC high level synthesis will often result in good results only if you stick to very similar patterns, effectively obliterating any advantage in using a higher level language. In any case, SystemC is a poor choice for implementing a processor.

  4. Architecture is a very broad term that is not limited to the ISA, in fact in modern processors ISA design is only a small piece of the puzzle. In the context of the design of a system, architecture usually means the set of system-level choices (e.g. can the DMA be controlled by any core or just one special one? Is the L1 cache fully or set associative? Do you have a cache at all, or manage memory in SW?), including the ISA and also the processor micro architecture . I think what your friend meant is that you are exploring various configurations of your processor, which is in fact architectural exploration (or micro architectural exploration if you prefer). However, he might have missed the fact that you are going to implement this on an FPGA, which makes the SystemC option nonsensical.

  5. This is wrong. If you are designing a very simple accelerator, such as a streaming filter, that might be true because HLS tools allow to easily insert pipeline stages, whereas you would have to do that manually in RTL (or use datapath retiming, but I think that's not possible in Vivado). In all other cases, and especially in a highly complex and structured object such as a processor, HLS will result in bloated, undebuggable and often plain wrong Verilog that then has to be synthesized - the tools are simply not designed for this job.

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  • \$\begingroup\$ Thank you for the help. I have already started the project using Verilog, but I still learned a lot form your answer! \$\endgroup\$ – Andrés AG Apr 8 '15 at 8:42
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You're at university and studying (presumably) to be an engineer. As an engineer you should understand how things work at a low level. In order to achieve this you need to strip away layers of abstraction, not add them.

For this reason, my advice is that you don't use SystemC for this project. You may end up using it in your professional career, but that's for the future.

If you choose to use it anyway then you should speak to your lecturer first. When I did a similar task at university, we were explicitly told not to use SystemC for the reason that I've outlined above.

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Lets be honest, it is all programming. What you can do in SystemC, you can also program in VHDL or Verilog. It is just a matter of tool support. It does not take SystemC or SystemVerilog.

If vendors what the obvious solution to convert RTL designers to System programming, they simply need to provide support the appropriate language for FPGA design. According to the Mentor 2012 Wilson survey, the language for FPGAs is VHDL. See http://blogs.mentor.com/verificationhorizons/blog/2013/08/05/part-8-the-2012-wilson-research-group-functional-verification-study/

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SystemC is used for complex designs. For e.g. Specifying something at architectural level. Advantage being, less lines of code than Verilog designs, Faster simulation time, Cycle accurate models. Don't believe person saying that SystemC is "not" synthesizable. Of course it is. To give you an idea, In Verilog we have level of abstraction, you can model with switch level/behavioral level. Choice is made based on complexity of design.

More familiar way for describing hardware is using Verilog, synthesis of which is supported in many EDA tools.

Typically for larger designs SystemC models and testbench are designed by architecture designer. These models then given to electronics designer to convert them into RTL using Verilog/VHDL.

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