I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and run it in an FPGA. Everything is going well so far, I started implementing the design in Verilog HDL a few days ago and got a very simple version working. Now the problem: I got in touch with some people that have been involved in hardware design for years and they suggested that before I go any further I should shift to using SystemC for the implementation. Now, made me very very confused because this was my thought:
Verilog -> As an HDL language specifically targets hardware design. Has some levels of abstraction like structural and behavioural Verilog, but it is a very neat form of specifying the RTL of a design. You can definitely synthesise it using a bunch of tools depending on the FPGA you choose (in my case I am using Xilinx Vivado 2014 and Zynq boards). On the down side plain Verilog does not offer enough abstraction for verification and that is why you have stuff like System Verilog.
SystemC -> This is a C++ class library that effectively introduces the concept of time in C++ and allows you to do an event driven simulation. Clearly it is a lot more high-level than any HDL and things here can be implemented much quicker. This makes it a very good tool for stuff like verification and even implementation of simulators so that people can start designing drivers and things for a chip before the thing is actually manufactured. Apparently, there is also a subset of SystemC that is synthesisable (I think even Xilinx Vivado can do this) and in some cases it enables SystemC to be used to design very large systems where a higher level of abstraction is handy.
So, my questions are:
- Are these notions of what systemC and Verilog (or HDL languages if you like) correct?
- When should I use SystemC and when Verilog?
- I am told that even in Verilog, using a lot of behavioral code can be a bit problematic in critical sections of the implementation because you are basically giving a lot less constrains to the synthesis tool on how to synthesise it. With a higher level of abstraction wouldnt this be a problem? i.e. If i use systemC I might end up with a very slow, power hungry, large design...
- The person that suggested SystemC mentioned that it looks like I am doing "architectural exploration" and that is why he would prefer Verilog. What exactly does that mean? I was under the impression that the architecture typically refers to the instruction set and the microarchitecture to an implementation of an instruction set (so the microarchitecture is the actual rtl that executes the instructions). So does architectural exploration mean that he thinks I am implementing a processor to see how feasible an instruction set is?
- He said that an argument for using SystemC is that its a lot easier because it is higher level of abstraction than an HDL. He also claimed that it was easier to get the timing of the design right. To what extent is this true?
Help would be greatly appreciated, I am a bit confused and finding it difficult to get clear information about this online. Thanks!