VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though.
What are some things which are easier to do in VHDL but not so easy or even impossible to do in Verilog? I just want to understand how they compare.
I just wonder that if one is as good as the other then why not just use one of the two and simplify the job of the EDA vendors that create tools to simulate and synthesize these HDLs and also the job and life of many other people?