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VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though.

What are some things which are easier to do in VHDL but not so easy or even impossible to do in Verilog? I just want to understand how they compare.

I just wonder that if one is as good as the other then why not just use one of the two and simplify the job of the EDA vendors that create tools to simulate and synthesize these HDLs and also the job and life of many other people?

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  • \$\begingroup\$ Rephrasing your last paragraph - if one is better than the other, why to use the worse one? There is a plenty of programming languages, several HDL's, numerous software for doing the same tasks and it is really the user/developer preference of what to use, considering different tradeoffs. \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 22:11
  • \$\begingroup\$ I find Verilog much easier to write in, but VHDL is very popular. It's really just a matter of taste; if you have serious OCD then use VHDL, if you to be productive then use Verilog. Also, schematic capture is a waste of time. \$\endgroup\$ – markt Feb 19 '15 at 22:36
  • \$\begingroup\$ @markt Schematic capture might be useful for top level interconnection and block diagram demonstration to the management :) \$\endgroup\$ – Eugene Sh. Feb 19 '15 at 22:38
  • \$\begingroup\$ @EugeneSh. Fair call :) but in engineering terms it's a waste of time. \$\endgroup\$ – markt Feb 19 '15 at 22:41
  • \$\begingroup\$ Hmm, yes, in a professional setting, a waste of time. In my masters program, taking a digital systems class for fun, I always finished our assignments using schematic capture faster than my classmates (who were in that concentration so had learned VHDL) who did the work in VHDL. So...I'd say go with what works for you, just ensure you at least learn Verilog or VHDL too. \$\endgroup\$ – iheanyi Feb 20 '15 at 22:30
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VHDL borrows from Ada, and its strongly typed compared to Verilog. Simple things are easier to do in Verilog, but complex things are easier to do in VHDL. Both can get the job done. Verilog does let you use the C preprocessor which is nice sometimes compared to generics.

Nothing is impossible in either.

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* Wrong Answer Starts *

The Reuse Methodology Manual has a section on recommended HDL coding style and a more specific one about VHDL to verilog translation. What I remembered the most is that "generate" statements should be avoided when writing for reuse because they have no equivalence in verilog.

* Wrong Answer Ends *

The user TM90 pointed in a comment below that the generate block does exist in Verilog. My answer is wrong.

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  • \$\begingroup\$ See IEEE Std 1364-2001, IEEE Standard Verilog® Hardware Description Language, 12.1.3 Generated instantiation. Notice the "Do not use generate statements. There is no equivalent construct in Verilog" is in the 2002 (currrent, 3rd edition) of The Reuse Methodology Manual as well as the 2nd (1999). \$\endgroup\$ – user8352 Feb 26 '15 at 1:03
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    \$\begingroup\$ There is definitely a generate Block in Verilog 2001. See sutherland-hdl.com/online_verilog_ref_guide/… 9.0 Generate Blocks \$\endgroup\$ – TM90 Mar 5 '15 at 10:37
  • \$\begingroup\$ One of the things I have found is that verilog allows one to do more lower level description, going down to transistors themself. This is not possible using VHDL. \$\endgroup\$ – quantum231 Mar 9 '15 at 21:31

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