I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to optimize having full macrocell and function block inputs.

How do I maximize the optimization to allow this to fit? (The following picture is what it looks like when it's compiled for the next size up

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    \$\begingroup\$ Without entering too far into analyzing the tables, note that the reason to move to a different FBs, while the others are not yet full in terms of macrocells, might be that some other resources of that FB are not sufficient - like inputs/outputs, terms (control/product), timing constraints. Refer to this document: xilinx.com/support/documentation/application_notes/xapp444.pdf \$\endgroup\$
    – Eugene Sh.
    Feb 20, 2015 at 20:24
  • \$\begingroup\$ @EugeneSh. I've taken a look at the document, and I guess my main question is what aspects of it I should focus on. It's true it might be too big, but it doesn't overuse any of the resources so there might be one way that could fit. I've tried the easy stuff of increasing the FB product limits, does that mean my only other real option is to do the exhaustive feature? \$\endgroup\$ Feb 20, 2015 at 20:47
  • \$\begingroup\$ I don't really have any specific suggestion beyond this one, since only you know the details of your design. Maybe the good starting point would be to look at the technology/RTL schematics generated and actual fitting of the blocks and thinking how YOU can optimize it.. \$\endgroup\$
    – Eugene Sh.
    Feb 20, 2015 at 20:52
  • \$\begingroup\$ For example, note that in the smaller chip, the two FBs that are not full each have only two inputs available. But in the larger chip, there's no FB that requires less than 3 inputs -- even the ones that use only one macrocell and one p-term. This suggests that FB inputs is the limiting resource for this design. \$\endgroup\$
    – Dave Tweed
    Feb 20, 2015 at 23:04


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