# MOSFET and Driver. Gate current questions

I am designing a three phase bridge inverter and I have some questions about the MOSFET driver. My MOSFET has a total gate charge (Qg) of 200 nC and a internal gate resistance of 2 ohm. I want it to switch in 200 ns (the PWM frequency will be 50 kHz, I think 1/100th is okay for turn on time isn't it?)

According to this formula, Ig = Q/t. I need 1 A. If I feed my driver with 15 V, I need a 13 ohm resistor between its output pin and MOSFET gate. (15 V / (13 ohm + 2 ohm) = 1 A).

Is it correct? Am I doing something wrong?

Also A last question. I am powering the drivers by using a LDO

Page 4. Current limit plot.

I'll have an input output differential of 15-20 V so 1.5 A of output current. Is it maximum peak current? or average. How can I know if it can provide a peak current high and fast enough as my driver needs?

Thank you.

The calculation method is close enough to OK to be OK. But you may have made a very bad assumption re required switching speed.

Examination of your formula and situation will make it clear that the current is the average gate current while the gate capacitor is charging (OR discharging).

The average current = Q.f = Ig.t.f
where t is charge time and f is number of gate turn-ons/second.

The LMx17xx family are not LDOs by any normal meaning of the term. It's probably not too important here.

As above, the figures for current is mean current during turn on.
IF you turned the MOSFET on at 50 kHz and
turn on time = 200 nS
and I_gate_average = 1A
Then Imean = Ig.t.f = 1 x 2E-7 s x 50000 = 10 mA average.
A suitably sized capacitor at the regulator output would probably suffice and allow the regulator to be very understressed.

Be sure that when you say 50 kHz you mean that that is the number of times per second that the FET is turned on.

Also note that at 50 kHz your PWM "frame period" = 1/50 kHz = 20 uS BUT if your PWM can run down to 1% duty cycle then an on time for the shortest bit is 20 uS/100 = 0.2 uS = your design charge time.

Tmin_on = 1/frame_frequency x minimum_duty_cycle.

Why are you using the HV part?
usually the regulator is fed from a supply slightly above Vout.
In most cases the HV part would be over over kill.
If it is needed it suggests that you are trying to do something "tricky".

Be sure your MOSFET gate can tolerate 15V.

Put a reverse biased zener gate to source close to MOSFET with minimum lead and track lengths. Vzener > Vgate_drive_max and < to << Vgate_abs_max. This clamps the gate safely against eg Millar capacitance drain transients. Theoretically not needed with pure resistive load. I ALWAYS fit one. Certainly a good idea with an inverter.

Overkill - reverse biased small Schottky gate to source same as zener. If gate rings the SChottky clamps negative half ringing cycle and eats ringing energy.

Be sure to have turn off gate drive that is about as aggressive as turn on drive.

• Hi Russell. Thank you for your answer. Yes I mean 50kHz PWM frequency. You are right that it won't work at 1% duty cycle. However I'm planning it to work at higher duty cycle (around 20%-70%). So in the worse case it will be still 20 times faster. Feb 22, 2015 at 10:48
• About the average current. I meant the average current supplied by the LDO. 1 A while the gate capacitor is charging, almost 0 while it's already charged. So if it's charging 1/100th of the PWM frequency (50kHz) at 1A, it will be around 10 mA of average current. It's not that much current, however it is a quite high peak current. That's my doubt about what LDO I should use. Feb 22, 2015 at 10:48
• Hi Russell, thank you for this update. I used 15v in order to minimize Vin and Vout difference in the LDO (Vin is 24v) so I can get more current. My MOSFET can tolerate it, however it's ture it's almost in the limit. Good advice about the reverse biased diodes. I had the zener diode, but never heard about the Schottky one. Thank you. Feb 22, 2015 at 11:11
• @zapeitor Re your "It's not that much current, however it is a quite high peak current. That's my doubt about what LDO I should use." -> see above where I write " ... A suitably sized capacitor at the regulator output would probably suffice and allow the regulator to be very under-stressed." Feb 22, 2015 at 12:38
• I knew about the zener trick, but never really understood the reasoning behind it, hadn't thought of Miller capacitor. Definitely going to scribble that down in my little notebook. Nice explanation. Feb 22, 2015 at 13:05