How can I find Gate Delay for bit 1 of the sum by a 4-bit look-ahead carry adder?

• Take the circuit diagram an find the logest path from that input to an output. Commented Feb 24, 2015 at 16:50
• google.co.in/… This is the diagram but i am not able to figure out can you explain me? Commented Feb 24, 2015 at 16:58
• I have seen the diagram C1 is found after 3 gate delays and then to find S1 1 more delay will add. So the answer to this will be 4 gate delays. Am i right? Commented Feb 24, 2015 at 17:11
• I dunno, because you did not show (liked to) a gate-level circuit of the adder you refer to. Without such a circuit the question can't be answered. (But I very much doubt 4 is the correct answer.) Commented Feb 24, 2015 at 17:56
• @WoutervanOoijen I sent the link in the comment. The first full adder will give C1 so find C1 the first adder will take three delays and then as the second full adder gets C1 it will find S1 in one delay so the net delay will be 3+1=4. If you know this then please correct me. Commented Feb 24, 2015 at 18:01