I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim.
All the instantiated IP blocks such as ALTFP_DIV, ALTFP_LOG, ALTFP_ADD_SUB are producing no outputs (result being "z"). The input signals for these blocks such as clock, clk_en and aclr are set properly.
I'm not sure if i'm missing any special steps here simulating the IP blocks.
My procedure in setting up this simulation is as the following:
- Turn on modelSim
- Create new project under a new arbitrary directory
- Add existing files from my own project that is written in Verilog (a bunch of .v files including the IP core instances)
- Compile on modelSim, all files get green checks (indicating fine)
- Start simulating by choosing the top level module -- loads and I can view the waveforms of some signals. My own code tend to have expected values but the connections to the output of these IP core modules give "z".
Final point: There are files associated with the creation of these IP core through megaWizard. names such as ADD_SUB_BB, ADD_SUB_INST. They core_name_bb.v files are green checked in compilation on modelSim while the core_name_INST.v files don't go through so I just excluded these files from the project tab listing on modelSim (not sure if that's the factor).
Any pointer would be much appreciated!