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I need things to happen at precise (down to the clock, ~5.5ns at 180MHz) periods of time based on a list; let's say 5 periods of 444444, 555555, 666666, 777777 and 888888 timer clocks (obviously a 32bit timer clock).

I propose the following:

  1. I set TIM2 "TIM_Period" with the first period. I set clock to system clock. I set it to trigger itself (is that possible?). I also set up an ISR to get fired at same time
  2. I start TIM2.
  3. I pre-load the next "TIM_Period" in the timer, somehow that it will only be "effective" after it "fires/updates".

  4. In ISR I increment an index through the array of values: If a next value exists I pre-load it into "TIM_Period" so TIM2 loads it next time. If no next value I turn off the self triggering. Other things might be done in the ISR as long as short enough to end before next timer firing.

If this works, could I (in the ISR, based on some list) also set up other timers to be triggered by this main timer?

Thank you for answers so far but soft timers are out of the question. Also, I don't need many; I need 3-4. I'd prefer hard answers from somebody that actually did trigger one timer from another.

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I'm not sure what exactly you mean by "triggering itself", do you mean up- or down-counting, from a fixed clock?

I have not done this myself, but if I'm understanding your question correctly then you're looking for the auto-reload register (ARR). The counter can be configured to be reset once it reaches the ARR value, and this also sets an event flag (UDE or UIE bit in TIMx_DIER). You can service this flag either in an ISR or with a DMA channel, each time updating ARR from a table of periods. "Stopping" can be achieved with ARR = 0.

Also see ST's appnote AN4013 about the STM32 timers, which includes example setups for some common use cases.

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Well, there are a couple of considerations here. This is certainly a sensible solution. However, the real question is how much granularity do you need in your timer periods? Hardware timers are a scarce resource, so it might be worth looking at creating virtual timers in software. A very common technique is to create 'scheduled tasks' with an ISR running at fixed intervals of, say, 1 kHz. Then what you can do is have some counters in software that you update in the ISR. Every time the ISR runs, you go through and decrement the counters. If one hits zero, then you perform some task and set the counter to a new delay value. This new value could be constant, or it could come from an array or elsewhere. This technique means you don't have to update the timer period all the time, and you can keep track of a large number of scheduled tasks. However, the flip side is that your timer tick becomes whatever the timer period is. This method would work well for simple things that need to take place around 100 times per second or less.

If you have ever used an Arduino; this is the technique used by the standard library to provide milis and run all of the delays accurately.

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    \$\begingroup\$ Hardware timers are far from a scarce resource on an STM32F4! Minimally, there are 6 16-bit timers and 2 32 bit timers. The 407 has 12 16-bit and 2 32-bit. In fact, because two of them are 32bit, and because of the flexibility involved in the timer flag, I find them much easier to use than on PICs. There's no need to juggle between how long they can count w/o rolling over and their precision. \$\endgroup\$ – Scott Seidman Feb 25 '15 at 23:58
  • \$\begingroup\$ What if I need to schedule 100 different small tasks? The larger chip you mention only has 14 timers. It's trivial to make a 100 element array of counters in software and handle that in an ISR. So long as you don't need to run ALL 100 tasks in the same timer tick, it's fine. Perhaps I should replace that 'are' with a 'can be'. Sometimes it makes sense to do it in hardware, sometimes it makes sense to do it in software. \$\endgroup\$ – alex.forencich Feb 26 '15 at 1:03

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