Your schematic is largely OK, with these issues:
- Lose D1. It is doing nothing useful. You already have a only 3.3 V to switch the FET with. D1 will eat up another 600 mV or so. Just direct connect the digital output to the gate of the PFET. R1 is still a good idea since that will keep the FET off during startup before the pin is actively driven one way or the other.
- Make sure the FET can switch well enough with only 3.3 V gate drive. There are certainly FETs that can do this, but it is not something you expect a randomly picked FET to do.
- Check the FET's on resistance with 3.3 V gate drive. Make sure the voltage drop caused by that times the 100 mA current is acceptable.
Russell pointed out that the digital signal to control the gate is 0-5 V. I guess that you think the diode is there to protect the gate from reverse voltage. That is very likely unnecessary. As always, read the datasheet for the parts you are using. 1.7 V reverse on the gate is probably fine.
If you're worried about the processor dumping current onto the 3.3 V line thru R1, then make R1 bigger. It only functions when the processor pin is not driven, which should only be for maybe a few 10s of ms while the processor starts up and before the firmware gets around to driving the pin one way or the other. Does it matter if the bluetooth module powers up and draws 100 mA for a few 10s of ms at power up? If not, then you can leave off R1 altogether. Since both the FET gate and the processor output will be high impedance when the processor pin is configured as input, a rather high value resistor will do. 100 kΩ should be fine. Probably even 1 MΩ would be fine, but check the input pin leakage current in the processor datasheet.