Two nets on my PCB need to be matched to within 100 mil, preferably 50 mil.

Currently I am doing this (see below); they are matched to about 10 mil.

(Trace length image)

However I am worried about whether I am Doing It Right (TM). Is there a better way?

I am using gEDA/PCB which unfortunately doesn't have an auto trace length matcher, but it does have a trace length calculator which is good enough for matching these.


Your signals look to be buried "within" a ground pour. This will affect propagation delays compared to if they are just running over a reference plane. Do you have a solid plane on the adjacent layer? Were the calculations of acceptable mismatch done with this in mind?

Actually, do you really need to match that accurately? Is this some spec handed down from on high by a silicon vendor?

50mils is a tiny difference in terms of time-of-flight. I'm a metric-head, 40mils is ~1mm. signals travel at ~60% of speed of light. 1mm is single-digit pico-seconds!

I've personally designed board with 125MHz DDR RAM with much less tight matching than that and had plenty of margin when I tested.

Get a copy of Black Magic for lots of practical advice on this sort of issue. Also read the si-list.

Regarding 90 degree bends, there's a fair bit of evidence that at sub-10GHz the signals don't actually see them. For example (from si-list) this thread:


There's a lot more to it than just "matching lengths", as actually what needs to be done is to match "flight-time", which is a whole bigger ball game.

  • \$\begingroup\$ Wow. Didn't realise it was small, I think I just made four orders of magnitude error (used km/s for c instead of m/s... not sure how...!) The two signals drive a video output buffer (2 bits/pixel.) They should be within 10 ns to get a good image. \$\endgroup\$ – Thomas O Jun 21 '11 at 12:31
  • \$\begingroup\$ The traces are inside a ground plane. The board is 2-layer; the top layer is a power plane, 3.3V. I'm not encountering issues with prototypes at the moment, but are there any particular issues this might cause? \$\endgroup\$ – Thomas O Jun 21 '11 at 12:32
  • \$\begingroup\$ 2-layers needs serious understanding of what's going on for high-speed stuff. It can be done, but it involves lots of work to validate it. low res video, you might get away with it. Drop me an email if you'd like a more in-depth discussion than this format allows for :) \$\endgroup\$ – Martin Thompson Jun 21 '11 at 16:14

The stub that sticks out towards the other trace isn't a good idea. Make your serpentines not as tight.

  • \$\begingroup\$ Aren't right angles worse than 45 degree turns? \$\endgroup\$ – kenny Jun 20 '11 at 23:41
  • 1
    \$\begingroup\$ Agreed with Brian and Kenny. If these traces are carrying signals which have a spectral content which includes any frequency greater than (speed of light) / (10 x trace length), then do 45 degree traces. If it is low speed stuff, you are probably OK. \$\endgroup\$ – Vintage Jun 21 '11 at 0:11
  • \$\begingroup\$ Well, even 45' turns will have some reflection. Use round corners if your EDA software can do that. \$\endgroup\$ – BarsMonster Jun 21 '11 at 8:22

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