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enter image description hereI am trying to create a logic circuit using only NAND Gates for this expression: (NOT Q AND P) OR R

This question has really gotten me stuck! Can somebody please help?

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    \$\begingroup\$ Have you learned DeMorgan's laws yet? \$\endgroup\$ – Ignacio Vazquez-Abrams Feb 28 '15 at 15:31
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    \$\begingroup\$ @IgnacioVazquez-Abrams - Yes i have - i have done other expressions but this one has really gotten me confused and im not sure why - i have added a picture of what i have done so far \$\endgroup\$ – Mathematica Feb 28 '15 at 15:39
  • \$\begingroup\$ Why are you drawing anything? Get the equation first. \$\endgroup\$ – Ignacio Vazquez-Abrams Feb 28 '15 at 15:43
  • \$\begingroup\$ @IgnacioVazquez-Abrams - I got the first bit but i thought if i draw something i should be able to understand the rest - im unsure on how to convert OR R to the nand bit \$\endgroup\$ – Mathematica Feb 28 '15 at 15:44
  • \$\begingroup\$ That's what DeMorgan's laws are for. \$\endgroup\$ – Ignacio Vazquez-Abrams Feb 28 '15 at 15:45
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The best way for a beginner is to think about each term separately and how you would create that with a NAND gate.

Let's start with the basic NAND gate truth table:

A | B | Q
---------
0 | 0 | 1
1 | 0 | 1
0 | 1 | 1
1 | 1 | 0

Now let's look at each term. We have a NOT, and AND, and an OR in there. So, how can we make those with NAND gates? Start with the NOT.

How does a NAND look like a NOT? Simple - when both inputs are the same. If you tie A and B together so they always see the same signal, then you have a NOT gate. 0 nand 0 = 1, 1 nand 1 = 0. So the NOT gate can just be:

schematic

simulate this circuit – Schematic created using CircuitLab

Next the AND. What's a NAND? It's an inverted AND. And AND with a NOT after it. So we just want to get rid of the NOT, and you can do that by adding another NOT:

schematic

simulate this circuit

Then comes the OR. Look closely at the NAND table and compare it to the OR table:

A | B | Q
---------
0 | 0 | 0
1 | 0 | 1
0 | 1 | 1
1 | 1 | 1

Do you see a similarity? If you were to invert the A and B values the table would instead look like this:

A | B | Q
---------
1 | 1 | 1
0 | 1 | 1
1 | 0 | 1
0 | 0 | 0

And that's the same sequence for Q as the NAND gate. So an OR gate is just a NAND gate with the inputs inverted. And we know how to invert already. So the OR looks like:

schematic

simulate this circuit

So now you know what the gates look like you can put the whole thing together:

schematic

simulate this circuit

However there's too many gates there. It can be simplified. The bit I have marked with a box - a NOT followed by a NOT - that's completely pointless (from a logic point of view) and is just wasteful. It serves no purpose. So you can get rid of it. Simplify to:

schematic

simulate this circuit

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\$(\overline Q P) + R\$

\$=\overline{(\overline {\overline Q P}) \overline R}\$

= (NOT Q NAND P) NAND NOT R

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  • \$\begingroup\$ Care to provide a short follow up narative? \$\endgroup\$ – Greg Hilston Feb 8 '17 at 19:56

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